Teru Yoneyama
Shizuoka University
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Publication
Featured researches published by Teru Yoneyama.
international symposium on circuits and systems | 2001
Shashidhar Tantry; Teru Yoneyama; Hideki Asai
In this paper, we propose two floating resistor circuits as synaptic weights for the implementation of analog neural networks. One among them has positive resistance and other has negative resistance. The floating resistor with positive resistance has a wider resistance range. In the same way, the proposed floating resistor with negative resistance is characterized by multiple negative resistance values. Both of these circuits are realized with the intention of using the same circuit for more than one number of synaptic weights. To check the compatibility of these circuits, the limit cycle generator, a type of analog neural network, is simulated with the proposed floating resistors as synaptic weights.
international symposium on circuits and systems | 2002
Takao Oura; Teru Yoneyama; Shashidhar Tantry; Hideki Asai
In this paper, we propose new bilateral floating resistor circuits having both positive and negative resistance values. The equivalent resistance of this floating resistor in CMOS technology can be changed by using controlled-voltages, which is an advantage over polysilicon or diffused resistor in the integrated circuit. Moreover the characteristics of the proposed circuits are independent of the threshold voltage. We have simulated the proposed circuit by using HSPICE. Finally, we have confirmed that the proposed circuit is useful as an analog component.
asia pacific conference on circuits and systems | 2002
Shashidhar Tantry; Takao Oura; Teru Yoneyama; Hideki Asai
In this paper, we propose a low voltage-floating resistor having both positive and negative resistance values. The circuit uses only two transistors between the supply voltages, which enables the circuit to operate at low supply voltages. The gate terminal is used in this circuit for the current addition/subtraction at input/output terminals of the floating resistor. As a result, it is possible to make the current flow even if power supply voltage is reduced. The characteristic of the proposed circuit is verified using HSPICE for the power supply /spl plusmn/1.5 V.
international symposium on neural networks | 1998
Teru Yoneyama; Hiroshi Ninomiya; Hideki Asai
The design of 3-valued neural networks with cyclic connections is described. First an efficient algorithm to analyze the continuous-time neural networks is proposed. Next, a 3-valued neural network with cyclic connection for the limit cycle generator is designed and simulated by the proposed algorithm and Spice. Finally, a switched capacitor-based limit cycle generator is designed and estimated.
international symposium on neural networks | 1999
Teru Yoneyama; H. Nonomiya; H. Asai
A design method of neural networks for limit cycle generator is described. First, the constraint conditions for the synaptic weights, which are given by the linear inequalities, are derived from the dynamics of neural networks. Next, the linear inequalities are solved by the linear programming method. The synaptic weights and other parameters are determined by the above solutions. Furthermore, the limit cycle generator is designed by analog neural networks and simulated by Spice. Finally, we confirm that our design method is efficient and practical for the design of neuro-based limit cycle generator.
international conference on electronics circuits and systems | 1998
Atsushi Kamo; Hiroshi Ninomiya; Teru Yoneyama; Hideki Asai
This paper describes a fast simulator for spatiotemporal pattern analysis of multivalued continuous-time neural networks, where the multivalued transfer function of a neuron is regarded as a stepwise constant function. Use of stepwise constant method enables one to analyse the state transition of the network without solving explicitly the differential equations. Furthermore, this method also enables one to select the optimal timestep in numerical integration. We have constructed a neural network simulator for the spatiotemporal pattern analysis and compared it with conventional simulators. Finally, it is shown that our simulator is faster and more practical than conventional simulators.
international symposium on neural networks | 2000
Teru Yoneyama; Hiroshi Ninomiya; Hideki Asai
We have proposed a design method of neural networks for limit cycle generator. The proposed method is based on the linear programming method. In this paper, we apply this method to the hysteresis neural networks for limit cycle generator. The hysteresis neuron has two threshold levels. Therefore the state of neuron can be flexibly controlled. As a result, the limit cycle, which can not be designed in the previous work, can be realized by the hysteresis neural networks. The behavior of this network is verified by our specialized simulator. As a result, we can easily design hysteresis neural networks for limit cycle generator.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 1998
Hiroshi Ninomiya; Atsushi Kamo; Teru Yoneyama; Hideki Asai
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 2003
Shashidhar Tantry; Yasuyuki Hiraku; Takao Oura; Teru Yoneyama; Hideki Asai
european solid-state circuits conference | 2002
Tsutomu Suzuki; Takao Oura; Teru Yoneyama; Hideki Asai