Teruhiko Kamigata

Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory

Multiprocessor system with high-speed exclusive control

Multithread executing method, multithread execution program and multithread execution apparatus

Instruction processing method for verifying basic instruction arrangement in VLIW instruction for variable length VLIW processor

Program performance analysis apparatus

Processing device for buffering sequential and target sequences and target address information for multiple branch instructions

Program load method, load program, and multi-processor

Method of and apparatus for creating load module and computer product

Method for loading multiprocessor program

Program performance analyzing apparatus