Teruhiko Yamada

An approach of diagnosing single bridging faults in CMOS combinational circuits

An approach of diagnosing single bridging faults in CMOS combinational circuits is proposed. In this approach, the cause of an error observed at the primary outputs is deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is proportional to [the number of gates]/spl times/[the number of tests], which is much smaller than that of the fault dictionary. The experimental results show that the CPU time is nearly proportional to the size of the circuit and the resolutions for most faults are less than 100, when using the tests to detect single stuck-at faults.<<ETX>>

A method of diagnosing single stuck-at faults in combinational circuits

A new method is proposed to diagnose single stuck-at faults in combinational circuits. In this method, based on the operations of the nonfaulty circuit, first the possible faulty paths are examined from the primary outputs, at which errors have been observed, toward the primary inputs to narrow down the suspected faulty section. Thea a fault simulation is conducted to deduce the fault location. According to the computational experiments it is expected that this method is faster than the conventional fault dictionary methods by about two orders of magnitude and the diagnosis time is almost proportional to the circuit size. Thus, this method is very effective for fault diagnosis of large-scale circuits.

Method of diagnosing single bridging faults in combinational circuit

A diagnosis method for single bridging faults in combinational circuits is proposed. In this method the cause of an error observed at the outputs is analyzed using a diagnosis table constructed based on the circuit and its test patterns. The size of the diagnosis table is proportional to the number of nets the number of tests and much smaller than the fault dictionary. The results of experiments conducted using the test patterns for single stuck-at faults show that the testing time is nearly proportional to the size of the circuit and that the number of possible fault locations can be reduced to 20 to 30. Hence, it is expected that by conducting fault simulations for those fault possibilities, a maximal resolution can be obtained within a reasonable amount of computation time.

Pseudorandom pattern built-in self-test for embedded RAMs

The self-test of built-in RAMs is an excellent method to simplify the testing of VLSI. This paper considers the built-in self-test using the linear feedback shift registers on the pseudorandom input generator and the output signature analyzer. It is demonstrated that the method is useful in testing RAM embedded in VLSI. First, the random test required for testing the functional faults of RAM is analyzed, indicating that the random test can be applied to the embedded RAM. Then a built-in self-test for the embedded RAM using the linear feedback shift registers is proposed. Finally, the fault-detection capability of the proposed test method is demonstrated by a computer simulation.

On testing of Josephson logic circuits consisting of RSFQ dual-rail logic gates

We have specified typical fabrication defects of the rapid single-flux-quantum (RSFQ) based logic gates, and then investigated the behavior of defective gates by SPICE simulation to estimate the defect coverage of logic testing. The simulation results show that the logic testing based on the stuck-at fault model can achieve at most 65% defect coverage for pulse-driven dual-rail RSFQ logic circuits and the defect coverage may increase up to 80% by properly adding two-pattern tests to the stuck-at fault tests.

A method of diagnosing logical faults in combinational circuits

The authors propose a method of diagnosing any logical fault in combinational circuits. The basic idea of the method has been obtained from an observation that only an error generated on one of the fault-nets propagates often to the primary outputs under a given test though more than one fault-net exist in the circuit under test. In this method, the fault-nets are located through a repetition of deducing candidates for each individual fault-net under the assumption of single fault-net and ascertaining which is the real one by probing. Probing internal nets is done only for finding the real fault-nets from these candidates. Consequently, it becomes possible to greatly decrease the number of probed nets. Preliminary experimental results show that fault locations are almost completely identified by probing 20% of the nets at most.<<ETX>>

Identification of redundant crosspoint faults in sequential PLAs with fault-free hardware reset

We present a technique for identifying redundant crosspoint faults in, sequential PLAs with fault-free hardware reset. This technique can find most redundant crosspoint faults efficiently. Experimental results show that about 7% of crosspoint faults are redundant on an average in the sequential PLAs synthesized by a commercial design tool SYNARIO for MCNC LGSynth89 finite-state machine benchmarks.

On current testing of Josephson logic circuits using the 4JL gate family

This paper discusses limitations of logic testing and capabilities of current testing for logic circuits consisting of the current injection logic gates with four Josephson junctions (4JL gates). We have specified typical fabrication defects of the 4JL gates, and then investigated the voltage and current behavior of defective gates by SPICE simulation to evaluate the defect coverage achieved by logic testing and current testing. The simulation results show that almost half defects cannot be detected by logic testing while more than 90% defect coverage is achievable by monitoring power supply current under multiple test vectors. We have also proposed a current testing scheme for Josephson combinational circuits.