Koji Yamazaki

Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines

Under the modern manufacturing technologies, the open defect is one of the significant issues to maintain the reliability of DSM circuits. However, the modeling and techniques for test and diagnosis for open faults have not been established yet. In this paper, we give an important clue for modeling an open fault with considering the affects of adjacent lines. Firstly, we use computer simulations to analyze the defective behaviors of a line with the open defect. From the simulation results, we propose a new open fault model that is excited depending on the logic values at the adjacent lines assigned by a test. Next, we propose a diagnosis method that uses the pass/fail information to deduce the candidate open fault. Finally, experimental results show that the proposed method is able to diagnose the open faults with good resolution. It takes about 6 minutes to diagnose the open fault on the large circuit (2M gates).

A Novel Approach for Improving the Quality of Open Fault Diagnosis

With the shrinking process technologies and the use of copper process, open defects on interconnect wires, contacts and vias often cause failure. Development of an efficient fault diagnosis method for open faults is desired. However, the diagnosis method for open faults has not been established yet. In this paper, we propose a novel approach for improving the diagnostic quality of open faults by introducing a threshold function in which the logical value of the line with open defect depends on the weighted logical values of its adjacent lines. By using the threshold function, we can deduce not only a faulty line but also an open defect site at the faulty line. Experimental results show that the proposed method can identify an exact faulty line in most cases with a very small computation cost. The proposed method can also identify the open defect site within 25%-length of the faulty line.

On the fault diagnosis in the presence of unknown fault models using pass/fail information

In this paper, we propose an effective diagnostic method in the presence of an unknown fault model, based on only pass/fail information on the applied tests. The proposed method deduces faulty conditions that are able to explain the behavior of the defect in the circuit and locates faulty sites, based on the number of detections for the single stuck-at fault at each line, by performing single stuck-at fault simulation with both passing and failing tests. As a result, we can derive a fault model from the faulty condition. To improve the ability of fault diagnosis, our method uses the logic values of lines and the condition whether the stuck-at faults at the lines are detected or not by passing and failing tests. Experimental results show that our method can accurately identify the fault models for 93% of faulty circuits and that the faulty sites are located within several candidates except for circuits with multiple stuck-at faults.

A method for diagnosing resistive open faults with considering adjacent lines

It is believed that resistive open faults can cause small delay defects at wires, contacts, and/or vias of a circuit. However, it remains to be elucidated whether any methods could diagnose resistive open faults. We propose a method for diagnosing resistive open faults by using a diagnostic delay fault simulation with the minimum detectable delay fault size. We also introduce a fault excitation function for the resistive open fault to improve the accuracy of the diagnostic result. The fault excitation function for the resistive open fault can determine a size of an additional delay at a faulty line with considering the effect of the adjacent lines. We demonstrated that the proposed method is capable of identifying fault locations for the resistive open fault with a small computation cost.

An approach of diagnosing single bridging faults in CMOS combinational circuits

An approach of diagnosing single bridging faults in CMOS combinational circuits is proposed. In this approach, the cause of an error observed at the primary outputs is deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is proportional to [the number of gates]/spl times/[the number of tests], which is much smaller than that of the fault dictionary. The experimental results show that the CPU time is nearly proportional to the size of the circuit and the resolutions for most faults are less than 100, when using the tests to detect single stuck-at faults.<<ETX>>

New Class of Tests for Open Faults with Considering Adjacent Lines

Under the open fault model with considering the effects of adjacent lines, the open fault excitation is depended on the tests. Therefore, the layout information is needed to generate a test for an open fault. However, it is not easy to extract accurate circuit parameters of a deep sub-micron LSI. We have already proposed an open fault model without using the accurate circuit parameters \cite{yanagi09, yamazaki09, tsume08}.In this paper, we propose a new class of the pair of tests for the open fault called Ordered Pair of Tests (OPT). OPT is generated based on the fault excitation function as a threshold function of the adjacent lines. Also we propose a method for generating OPTs from the given stuck-at fault test set. The proposed method generates OPTs using only information about adjacent lines of the target open fault. Experimental results show that the proposed method can generate the OPTs for the open faults with high fault coverage.

Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information

In general, we do not know which fault model can explain the cause of the faulty values at the primary outputs in a circuit under test before starting diagnosis. Moreover, under Built-In Self Test (BIST) environment, it is difficult to know which primary output has a faulty value on the application of a failing test pattern. In this paper, we propose an effective diagnosis method on multiple fault models, based on only pass/fail information on the applied test patterns. The proposed method deduces both the fault model and the fault location based on the number of detections for the single stuck-at fault at each line, by performing single stuck-at fault simulation with both passing and failing test patterns. To improve the ability of fault diagnosis, our method uses the logic values of lines and the condition whether the stuck-at faults at the lines are detected or not by passing and failing test patterns. Experimental results show that our method can accurately identify the fault models (stuck-at fault model, AND/OR bridging fault model, dominance bridging fault model, or open fault model) for 90% faulty circuits and that the faulty sites are located within two candidate faults.

A method of diagnosing logical faults in combinational circuits

The authors propose a method of diagnosing any logical fault in combinational circuits. The basic idea of the method has been obtained from an observation that only an error generated on one of the fault-nets propagates often to the primary outputs under a given test though more than one fault-net exist in the circuit under test. In this method, the fault-nets are located through a repetition of deducing candidates for each individual fault-net under the assumption of single fault-net and ascertaining which is the real one by probing. Probing internal nets is done only for finding the real fault-nets from these candidates. Consequently, it becomes possible to greatly decrease the number of probed nets. Preliminary experimental results show that fault locations are almost completely identified by probing 20% of the nets at most.<<ETX>>

A heuristic algorithm for reducing system-level test vectors with high branch coverage

We introduce a heuristic that generates as few a number of test vectors as possible with high branch coverage for the functional verification of digital design. The challenge is how to save time and effort for sufficient verification at system-level. We focus on generating test vectors from the circuit specification written in C. We reuse them to SystemC description by removing their redundancies while maintaining the branch coverage as is. Experimental results of our practical design show that over 90% on average of the redundant test vectors were reduced with 100% branch coverage maintained. The reused test vectors for SystemC Bus Cycle Accurate models scored 80% branch coverage on average. These results are significant for saving verification cost and beneficial for simplifying debugging works.

Effective Post-BIST Fault Diagnosis for Multiple Faults

With the increasing complexity of LSI, built-in self test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore the authors propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. The fault diagnosis based on the compressed responses from BIST was called the post-BIST fault diagnosis (Takahashi et al., 2005, Takamatsu, 2005). The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 (Sato et al., 2005) benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, the feasibility of diagnosing the large circuits within the practical CPU times can be confirmed. The feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis was proven