Tetsu Tanizawa

A 100 k-gate ECL standard-cell LSI with layout system

An ECL (emitter-coupled-logic) device that achieves 100 K-gate integration with a standard-cell-layout approach is described. A standard-cell CAD (computer-aided-design) architecture enables high-power ECL gate cells and freely placed megacells to be integrated on a chip with fixed-pattern power supply buses. The 3- mu m-thick top (fourth) metal layer is dedicated to the main power buses. Under the main power buses are densely packed polycells (polycell seas) and megacells surrounded by global chip routing channels and fixed-pitch subpower buses in the third metal layer and orthogonal to the main power buses. This structure gives the chip a density twice that of conventional ECL gate arrays and a more flexible layout without compromising high-power capacity. The die of the 60-W chip is 14.72 mm/sup 2/, with 100 K equivalent gates and a maximum gate density of 1255 gates/mm/sup 2/. The chip is mounted on the 561-pin PGA (pin grid array) package with TAB (tape-automated-bonding) leads and bumps on the die with 100- mu m pitch. The thermal resistance (junction-ambient) of the package is less than 1 degrees C/W at an air flow of 10 m/s, Maximum dissipation in this package is 60 W.<<ETX>>

Clock driven design method (CDDM) for deep sub-micron ASICs

A newly developed CDDM achieves Concurrent Top-Down Design Flow. CDDM handles clock tree in the beginning of the design stage, and solves clock skews perfectly. It supplies accurate clock performance before main layout. A unique T-Bar/Star routing and FF-Virtual Placement were adopted to ensure 165 ps maximum clock skew for Fujitsus 0.5 micron ASICs with no layout iteration.