Tetsuro Takizawa

High performance and cost effective memory architecture for an HDTV decoder LSI

This paper proposes an efficient memory mapping and a frame memory compression for an HDTV decoder LSI using Direct Rambus/sup TM/ DRAM (DRDRAM). The DRDRAM is employed to achieve the high memory bandwidth required for HDTV decoding at the minimum memory cost. The proposed memory mapping achieves a high memory bandwidth sufficient for HDTV decoding even in the worst case and no costly line buffers are required in the LSI for format conversion. The frame memory compression method reduces the memory cost by half and achieves HDTV decoding with a single 64 Mb DRDRAM chip without loss of memory access efficiency. Simulation results show that SNR degradation is 0.1 to 2 dB in the worst frame and no visible degradation is perceived except for a resolution chart sequence.

An efficient memory arbitration algorithm for a single chip MPEG2 AV decoder

This paper presents an efficient memory arbitration algorithm for a system on a chip. We have implemented the algorithm into a single chip MPEG2 AV decoder. According to simulations, the memory access efficiency of the arbiter based on the new algorithm is around 95% with a 32-bit 133 MHz SDRAM, while those of conventional arbiters are less than 80%.

Memory compression method considering memory bandwidth for HDTV decoder LSIs

This paper proposes a frame memory compression method for an MPEG-2 Main Profile@High-Level (MP@HL) decoder LSI using Direct RambusTM DRAM (DRDRAM). The compression method is based on two-dimensional adaptive DPCM (2-D ADPCM) and is designed to achieve efficient memory access. HDTV bitstreams are decoded with a single 64 megabit (Mb) DRDRAM without subjective image quality degradation. Computer simulation is performed for ten HDTV bitstreams encoded at 22 Mbps. Simulation results show that, in the worst case, SNR loss compared to the full spec decoder is 0.71 dB for a luminance, 0.27 dB and 0.57 dB for chrominances.