Hidenobu Harasaki

A real-time video signal processor suitable for motion picture coding applications

A real-time video signal processor (VSP) system has been developed. The system employs three multiprocessor clusters, each of which has 12 video signal processor modules (VSPMs). A VSPM in a cluster processes its assigned subimage by using an overlap-save technique. Each cluster uses the same multiprocessor structure, in which homogeneous processor modules are connected to input, output, and feedback buses in parallel and two bus switch units. By controlling these units, the clusters can be combined in pipeline and/or parallel forms. Each cluster also uses a variable delay unit which achieves up to one frame delay on the feedback bus. By using this unit, interframe processing can be carried out without using internal data memories in VSPMs for the frame delay. The employment of the bus switches and the variable delay unit increases flexibility for a variety of signal processing algorithms. The system performs 500 million operations per second and is currently used as a real-time evaluation system for low-bit-rate picture encoders. >

A simplified motion estimation using an approximation for the MPEG-2 real-time encoder

We propose a simplified motion estimation method which provides motion vectors for all types of motion compensation used in MPEG-2. The method is a result of applying a newly introduced approximation to the canonical three-step method described in the MPEG-2 Test Model. It reduces the number of necessary computations in the second and the third steps to less than 1%, and that of data transfers to about 8% of the canonical method. Total complexity of the proposed method is nearly that of the full-pel search motion estimation.

A microprogrammable real-time video signal processor (VSP) for motion compensation

A video signal processor (VSP) LSI circuit with a three pipelined architecture has been developed for pattern matching, which is fundamental for the motion compensation necessary for teleconferencing systems. A high-speed arithmetic logic unit with absolute-value calculation capability and a minimum/maximum value detector, which are essential to pattern matching, have been integrated on the VSP LSI. The chip was fabricated with a 2.5- mu m CMOS and double-layer metallization technology. The number of MOSFETs integrated on the 9.91*9.50-mm/sup 2/ chip is about 48000. It operates at a 14.3-MHz clock frequency with a single 5-V power supply and typically consumes 240 mW. An experimental video signal processing system, using a single VSP LSI chip, is discussed. >

Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP

A parallel signal processor architecture has been developed for real time motion picture encoding. The architecture is based on spatial parallelism utilization in a picture signal. Plural element processors handle subregional pictures simultaneously without communicating with other element processors. However, due to an overlapsave technique where every sub-picture input area is chosen to be wider than the output area, element processors can carry out continuous processing over an entire picture. In order to increase motion picture processing efficiency as well as system implementation simplicity, a specific element processor LSI chip, composed of a pipeline arithmetic unit, two dimensional address generators, a raster scan signal handler, and a sequence controller, has been developed by using more than 220,000 transistors. The developed parallel processor is shown to be applicable to a software programmable low bit rate TV codec.

A microprogrammable real-time video signal processor (VSP) LSI

A microprogrammable real-time video signal processor (VSP) LSI has been developed for constructing a parallel video signal processing system. The VSP LSI employs a flexible multistage pipelined architecture and can handle such sophisticated image signal processing as high-speed edge detection and motion compensation. It contains many operational function units such as an arithmetic logic unit and with absolute value calculation capability, a minimum/maximum value detector, a two-port SRAM, RAM address pointer and clocked bus lines. The VSP LSI has been designed using two different kinds of automatic layout programs. The chip, which was fabricated with a 2.5-/spl mu/m CMOS and double-layer metallization technology, has an area of 9.91/spl times/9.50 mm/SUP 2/ and contains about 48000 MOSFETs. It operates at a clock frequency of 14.3 MHz with a single 5-V power supply and typically consumes 240 mW. An experimental system, using a single VSP LSI chip, has been constructed in order to demonstrate various application capabilities, such as interframe difference operations, high-speed edge detection and motion compensation.

High performance and cost effective memory architecture for an HDTV decoder LSI

This paper proposes an efficient memory mapping and a frame memory compression for an HDTV decoder LSI using Direct Rambus/sup TM/ DRAM (DRDRAM). The DRDRAM is employed to achieve the high memory bandwidth required for HDTV decoding at the minimum memory cost. The proposed memory mapping achieves a high memory bandwidth sufficient for HDTV decoding even in the worst case and no costly line buffers are required in the LSI for format conversion. The frame memory compression method reduces the memory cost by half and achieves HDTV decoding with a single 64 Mb DRDRAM chip without loss of memory access efficiency. Simulation results show that SNR degradation is 0.1 to 2 dB in the worst frame and no visible degradation is perceived except for a resolution chart sequence.

Video signal processor configuration by multiprocessor approach

A real-time video signal processor (VSP), suitable for VLSI implementation, is proposed. In order to obtain software controllability for video signal processing in a real-time environment, the VSP employs a multiprocessor configuration, where a plural number of video signal processing modules (VSPMs) are connected to input, output and feedback buses. Each VSPM processes its own assigned sub-images without communicating from/to other VSPMs. As the VSP needs no overhead for VSPM communication, the number of VSPMs involved does not affect the VSP system performance. The homogeneous processor based approach, employed in VSP, will become the most suitable LSI implementation methodology in the near future, due to processor module regularity and system flexibility.

A realtime software MPEG transcoder using a novel motion vector reuse and a SIMD optimization techniques

A realtime software MPEG transcoder has been developed. Novel motion vector reuse and SIMD optimization techniques are introduced to accelerate the transcoder without any quality degradation. Mean absolute error approximation criteria are employed in the reuse technique to refine scaled motion vectors. The developed transcoder on a Pentium II 266 MHz machine runs 2.5 times as fast as realtime, when scaling an MPEG-1 bitstream to half size.

A real-time HDTV signal processor: HD-VSP

A programmable real-time high-definition television (HDTV) signal processor (HD-VSP) has been developed. For conventional TV signals, a previously reported video signal processor (VSP) has introduced flexible software control capability based on subregional processing. In order to expand such flexibility for real-time HDTV signal processing, the HD-VSP employs eight VSP clusters and programmable time-expansion/compression units. An input HDTV signal is converted to eight time-expanded subregional signals to reduce their sampling rate to that of conventional TV signals. The converted signals are then processed by the eight clusters in the same manner as the VSP. Therefore, programs developed for conventional TV signals can be applied to HDTV with little modification. Processed signals obtained from the eight clusters are time-compressed and multiplexed to reconstruct an output HDTV signal. This HD-VSP has 16 component processors per cluster and is capable of 2.5 giga-operations/s. Several coder programs, including a discrete cosine transform coder and an intraframe differential pulse code modulation (PCM) coder, are developed to evaluate HDTV coding efficiency. >

Theoretical background and improvement of a simplified half-pel motion estimation

This paper describes theoretical background of a mean absolute error (MAE) approximation method which was adopted as a half-pel motion estimation method in our real-time MPEG-2 codec VisuaLink 7000. We also propose an improved MAE approximation method which employs the horizontal and the vertical differentials of a source picture in addition to the MAEs of adjacent full-pel motion vectors. In general, any approximation method for MAE involves some loss of coding efficiency. However, the proposed method reduces loss of coding efficiency to 1/2/spl sim/3/4 of other existing methods with negligible increases of necessary computations and data transfers.