Tetsuya Suemitsu

Optical study of high-biased AlGaN/GaN high-electron-mobility transistors

Microscopic electroluminescence (EL) and photoluminescence (PL) measurements of high-biased AlGaN/GaN high-electron-mobility transistors are reported. We observed that the EL intensity reveals peaks around the edge of the channel and the electron temperature there is higher than the electron temperature at the center of the channel. These EL features were found to be consistent with the change in the junction temperature, which we locally estimated by comparing the PL data with measurements in raised ambient temperatures.

High-performance 0.1-/spl mu/m gate enhancement-mode InAlAs/InGaAs HEMT's using two-step recessed gate technology

Novel approach for making high-performance enhancement-mode InAlAs/InGaAs HEMTs (E-HEMTs) is described for the first time. Most important issue for the fabrication of E-HEMTs is the suppression of the parasitic resistance due to side-etching around the gate periphery during gate recess etching. Two-step recessed gate technology is utilized for this purpose. The first step of the gate recess etching removes cap layers wet-chemically down to an InP recess-stopping layer and the second step removes only the recess-stopping layer by Ar plasma etching. The parasitic component for source resistance is successfully reduced to less than 0.35 /spl Omega//spl middot/mm. Etching selectivities for both steps are sufficient not to degrade uniformity of devices on the wafer. The resulting structure achieves a positive threshold voltage of 49.0 mV with high transconductance. Due to the etching selectivity, the standard deviation of the threshold voltage is as small as 13.3 mV on a 3-in wafer. A cutoff frequency of 208 GHz is obtained for the 0.1-/spl mu/m gate E-HEMTs. This is therefore one of the promising devices for ultra-high-speed applications.

Improved Recessed-Gate Structure for Sub-0.1-µm-Gate InP-Based High Electron Mobility Transistors

An improved recessed-gate structure for high-performance short-gate InP-based InAlAs/InGaAs high electron mobility transistors (HEMTs) is presented. The effective gate length of the HEMTs is found to be related to the electron density in the side-etched region between the gate and the ohmic capped region. The higher electron density in the side-etched region is efficiently suppresses the effective gate length. A new gate recess process, which consists of a sequence of wet-chemical etching and Ar-plasma etching, enables us to reduce the effective gate length. The new recessed-gate structure successfully provides improved performance with high uniformity. A cutoff frequency of 300 GHz is achieved even with 0.07-µm-gate HEMTs.

Ultrahigh sensitive sub-terahertz detection by InP-based asymmetric dual-grating-gate high-electron-mobility transistors and their broadband characteristics

We report on room-temperature plasmonic detection of sub-terahertz radiation by InAlAs/InGaAs/InP high electron mobility transistors with an asymmetric dual-grating-gate structure. Maximum responsivities of 22.7 kV/W at 200 GHz and 21.5 kV/W at 292 GHz were achieved under unbiased drain-to-source condition. The minimum noise equivalent power was estimated to be 0.48 pW/Hz0.5 at 200 GHz at room temperature, which is the record-breaking value ever reported for plasmonic THz detectors. Frequency dependence of the responsivity in the frequency range of 0.2–2 THz is in good agreement with the theory.

Emission of terahertz radiation from dual grating gate plasmon-resonant emitters fabricated with InGaP/InGaAs/GaAs material systems

This paper reviews recent advances in our original 2D-plasmon-resonant terahertz emitters. The structure is based on a high-electron-mobility transistor and featured with doubly interdigitated grating gates. The dual grating gates can alternately modulate the 2D electron densities to periodically distribute the plasmonic cavities along the channel, acting as an antenna. The device can emit broadband terahertz radiation even at room temperature from self-oscillating 2D plasmons under the DC-biased conditions. When the device is subjected to laser illumination, photo-generated carriers stimulate the plasma oscillation, resulting in enhancement of the emission. The first sample was fabricated with standard GaAs-based heterostructure material systems, achieving room temperature terahertz emission. The second sample was fabricated in a double-decked HEMT structure in which the grating gate metal layer was replaced with the semiconducting upper-deck 2D electron layer, resulting in enhancement of emission by one order of magnitude.

Correlation between current–voltage characteristics and dislocations for n-GaN Schottky contacts

We directly evaluated the effect of dislocations on current–voltage (I–V) characteristics of Au/Ni/n-GaN Schottky contacts. A submicrometer Schottky dot array was formed by electron beam lithography, and I–V measurements were conducted using atomic force microscopy with a conductive probe. The sample, which has a free electron concentration of 5.8×1017 cm−3, showed that neither dislocations nor steps affect the I–V characteristics. These results indicate that, in fabricating short-gate FETs, gate Schottky contacts containing dislocations should not be considered a problem with respect to uniformity and reproducibility.

Current-driven detection of terahertz radiation using a dual-grating-gate plasmonic detector

We report on the detection of terahertz radiation by an on-chip planar asymmetric plasmonic structure in the frequency region above one terahertz. The detector is based on a field-effect transistor that has a dual grating gate structure with an asymmetric unit cell, which provides a geometrical asymmetry within the structure. Biasing the detector with a dc source-to-drain current in the linear region of the current-voltage characteristic introduces an additional asymmetry (electrical asymmetry) that enhances the detector responsivity by more than one order of magnitude (by a factor of 20) as compared with the unbiased case due to the cooperative effect of the geometrical and electrical asymmetries. In addition to the responsivity enhancement, we report a relatively low noise equivalent power and a peculiar non-monotonic dependence of the responsivity on the frequency, which results from the multi-plasmonic-cavity structure of the device.

An 0.03 μm gate-length enhancement-mode InAlAs/InGaAs/InP MODFET's with 300 GHz f/sub T/ and 2 S/mm extrinsic transconductance

We have developed high-performance enhancement-mode InP-based modulation-doped field-effect transistors with 0.03 /spl mu/m gate-length. A record high current gain cutoff frequency exceeding 300 GHz has been achieved, and the maximum extrinsic transconductance is as high as 2 S/mm with an associated drain current of 0.5 A/mm at a drain bias of 1 V. This high performance is a result of the reduction or gate length, the use of the high barrier metal Pt as gate electrodes, and most importantly the employment of the well-developed wet-etching technology that allows the formation of a very deep gate groove while retaining small side etching. The excellent E-MODFET performance opens up the possibility of implementing ever faster high-speed circuits based on direct-coupled FET logic.

An Optically Clocked Transistor Array for High-Speed Asynchronous Label Swapping: 40 Gb/s and Beyond

We describe the development of an optically clocked transistor array (OCTA) interface device for label swapping high-speed asynchronous burst optical packets. The OCTA integrates the three critical functions of serial-to-parallel (SP) conversion, parallel-to-serial (PS) conversion, and clock-pulse generation into a simple optoelectronic integrated circuit (OEIC) to create a single-chip interface between the input/output baseband optical labels and a CMOS label processor. The result is a high-performance label swapping solution which is compact and low power. In this paper, a detailed investigation of the design and optimization of the circuit is first performed, followed by testing of device stability under subsystem operating conditions. Finally, demonstrations of single-channel switching speeds allowing greater than 100-Gb/s operation, 40-Gb/s SP and PS conversion with an eight-channel OCTA, and error-free label swapping of 10-Gb/s asynchronous optical packets with a prototype label swapper module are described.

An intrinsic delay extraction method for Schottky gate field effect transistors

This letter reports a new method for extracting the intrinsic transit delay associated with the carrier transport under the gate of field-effect transistors (FETs). With this method, the parasitic charging time is ruled out by the de-embedding used to strip the pad parasitics. Therefore, the intrinsic transit delay and the drain delay associated with the extended depletion region toward drain electrode can be separated without the influence of the parasitic charging time, as proven by an analysis of short-channel InP-based high electron mobility transistors. The method is applicable to any type of Schottky-gate FETs and could be helpful for studying the effective carrier velocity in the gate region of FETs.