Tetsuya Uemura

Demonstration of a novel multiple-valued T-gate using multiple-junction surface tunnel transistors and its application to three-valued data flip-flop

A novel T-gate consisting of multi-junction surface tunnel transistors (MJ-STTs) and hetero-junction FETs (HJFETs) were proposed and its operation was successfully confirmed by both simulation and experiment. The number of the devices required for their-gate can be drastically reduced due to a high functionality of the MJ-STT. Only three MJ-STTs and three HJFETs were required to fabricate the three-valued T-gate, whose number is less than one half of that of the conventional circuit. The fabricated circuit exhibited a basic T-gate operation with various logic function. Furthermore, a multiple-valued data flip-flop (D-FF) circuit could be realized by only one T-gate.

Multiple-junction surface tunnel transistors for multiple-valued logic circuits

Multiple-junction surface tunnel transistors (MJ-STTs), in which gate-controlled multiple p/sup -//n/sup -/ tunnel-junctions are connected in series between the source and drain, are proposed for application as multiple-valued logic circuits. The transistor operation with four negative-differential-resistance characteristics is confirmed by fabricating a GaAs-based four-tunnel-junction MJ-STT. In addition, to demonstrate the increased functionality of these MJ-STTs, a tri-stable circuit is constructed with an MJ-STT and a load resistor connected in series. Three output voltages (states) are controlled by a reset pulse and successive input pulses applied to the gate of the MJ-STT, confirming the success of the tri-stable operation.

Large enhancement of interband tunneling current densities of over 10/sup 5/ A/cm/sup 2/ in In/sub 0.53/Ga/sub 0.47/As-based surface tunnel transistors

In/sub 0.53/Ga/sub 0.47/As-based Surface Tunnel Transistors (STTs), which control an interband tunneling current between an n-type channel and a p-type drain by an insulated gate, are investigated with the goal of increasing the tunneling current-density for high-speed operation. The fabricated devices enhanced an interband tunneling current density by a factor of 10/sup 2/ compared to the conventional GaAs-STTs due to a smaller bandgap energy and a lighter electron effective mass, and exhibited a clear gate-controlled negative differential resistance (NDR) characteristics with maximum tunneling current densities of over 10/sup 5/ A/cm/sup 2/. The cutoff frequency (F/sub T/) and maximum oscillation frequency (f/sub max/) of a fabricated device with a 1.0-/spl mu/m gate length were estimated to be 7.9 GHz and 20 GHz, respectively, in the NDR region.

A three-valued D-flip-flop and shift register using multiple-junction surface tunnel transistors

A three-valued D-flip-flop (D-FF) circuit and a two-stage shift register built from InGaAs-based multiple-junction surface tunnel transistors (MJSTT) and Si-based metal-oxide-semiconductor field effect transistors (MOSFET) have been demonstrated. Due to the combination of the MJSTTs latching function and the MOSFETs switching function, the number of devices required for the D-FF circuit was greatly reduced to two from the thirty required for the FET-only circuit.

MBE regrowth with hydrogen cleaning and its application for the fabrication of surface tunnel transistors

Abstract Regrown interfaces of GaAs and GaSb, which were prepared by hydrogen cleaning prior to molecular-beam epitaxy (MBE) regrowth, were characterized. Among various hydrogen cleaning methods explored in this study, the absence of carrier depletion around the interface was reproducibly obtained by cleaning with either hydrogen gas or its radicals. For p-AlGaSb/GaSb modulation-doped structures in which p-AlGaSb layers were regrown, proper accumulation of a two-dimensional hole gas at the interface was confirmed when cleaned with hydrogen radicals. This MBE-regrowth technique was then utilized to fabricate new transport devices, surface tunnel transistors (STTs), for which the quality of the regrown interface severely limits device operation. The STTs thus fabricated exhibited proper transistor characteristics.

Design and analysis of a novel quantum-MOS sense amplifier circuit

A novel quantum-MOS sense amplifier circuit consisting of resonant tunneling diodes (RTDs) as pull-up devices and NMOS transistors is discussed in this paper. Compared to the conventional sense amplifier circuits using CMOS technology, the proposed QMOS sense amplifier exhibits about 20% higher sensing speed. The cross-coupled QMOS latch, which is at the heart of the sense amplifier circuit, has metastable and unstable states which are closely related to the I-V characteristics of the RTDs. The stability analysis has been made by using phase-plot diagram and determining how RTD parameters relate to circuit speed. Robustness of the sense amplifier has been discussed.