Tetsuyuki Suzaki

Si bipolar chip set for 10-Gb/s optical receiver

Three Si bipolar ICs, a preamplifier, a gain-controllable amplifier, and a decision circuit, have been developed for 10-Gb/s optical receivers. A dual-feedback configuration with a phase adjustment capacitor makes it possible to increase the preamplifier bandwidth up to 11.2 GHz, while still retaining flat frequency response. The gain-controllable amplifier, which utilizes a current-dividing amplifier stage, has an 11.4-GHz bandwidth with 20-dB gain variation. A master-slave D-type flip-flop is also operated as the decision circuit at 10 Gb/s. On-chip coplanar lines were applied to minimize the electrical reflection between the ICs. >

A 60-GHz f/sub T/ super self-aligned selectively grown SiGe-base (SSSB) bipolar transistor with trench isolation fabricated on SOI substrate and its application to 20-Gb/s optical transmitter ICs

A 60-GHz cutoff frequency (f/sub T/) super self-aligned selectively grown SiGe-base (SSSB) bipolar technology is developed. It is applied to 20-Gb/s optical fiber transmitter ICs. Self-aligned bipolar transistors mutually isolated by using a BPSG-filled trench were fabricated on a bond-and-etchback silicon-on-insulator (SOI) substrate to reduce the collector-substrate capacitance C/sub CS/. The SiGe base was prepared by selective epitaxial growth (SEG) technology. A 0.4-/spl mu/m wide emitter was used to reduce the junction capacitances. The maximum cutoff frequency f/sub T/ and the maximum frequency of oscillation f/sub max/ were 60 and 51 GHz, respectively. By using this technology, Si-ICs for an optical transmitter system were made, such as a selector (a multiplexer without input and output retiming D-type flip-flops (D-F/Fs)), a multiplier, and a D-F/F. An internal high-speed clock buffer circuit achieves stable operation under a single clock input condition in the selector and the multiplier ICs. Their stable operation was confirmed up to 20 Gb/s. The selector IC for data multiplexing operates at over 30 Gb/s.

Si-analog IC's for 20 Gb/s optical receiver

This paper describes two kinds of Si-analog ICs, a preamplifier IC and a decision IC consisting of a gain-controllable amplifier and a D-type flip flop (D-F/F) for a 20 Gb/s optical receiver. A 20 Gb/s optical receiver for the generation beyond 10 Gb/s has been fabricated in hybrid circuit technology. However, the development of high-speed analog ICs operating at 20 Gb/s, making possible reduced system size, is indispensable for stable system operation in practical application. >

A 2.4 Gb/s receiver and a 1:16 demultiplexer in one chip using a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor

This paper reports a 2.4 Gb/s optical terminal IC that integrates high-speed analog and digital circuits for future optical networks using 60-GHz f/sub T/ self-aligned silicon-germanium (SiGe)-alloy base bipolar transistors. The selective epitaxial growth (SEG) SiGe base was formed by using cold-wall ultra-high vacuum (UHV)/CVD technology. Boron concentration reduction at the SiGe epitaxial layer/Si-substrate interface by using a new treatment prior to SEG leads to electrical characteristics with less dependence on bias voltage. The IC consists of a receiver (a preamplifier, an automatic gain control (AGC) amplifier, a phase-locked loop (PLL), and a D-type flip-flop (D-F/F)), and a 1:16 demultiplexer (DMUX). An input offset control circuit is included in the AGC amplifier for wide dynamic range. Trench isolation and silicon-on-insulator (SOI) technologies are introduced to reduce crosstalk between the amplifiers and the PLL. Power consumptions are 0.6 W at -5.2 V for the analog part and 0.45 W at -3.3 V for the digital part, which does not include the ECL output buffers.

2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8:1 multiplexers with a 0.15-/spl mu/m CMOS technology

This paper reports the first CMOS implementation of an 8:1 byte-interleaved multiplexer (byte-MUX) operating in the Gb/s region, together with an 8:1 bit-interleaved multiplexer (bit-MUX). A future generation 0.15-/spl mu/m CMOS technology has been applied. Both chips use identical bit-MUX cores with a static shift-register architecture, and have ECL interfaces with a single supply of -2 V. The byte-MUX demonstrates 43-mW/GHz dependence on clock frequency and operates up to 2.8 Gb/s with a power dissipation of 176 mW. The bit-MUX showed 20-mW/GHz dependence on clock frequency and operated up to 3.0 Gb/s with a power dissipation of 118 mW. This revel of performance has been achieved by a novel row-column exchanger configuration, critical path reduction and precise clocking techniques utilized in the bit-MUX core, and the development of high-speed I/O buffers.

A Si bipolar chip set for 10 Gb/s optical receiver

The development of a chip set comprised of analog circuits with a bandwidth exceeding 10 GHz and digital circuits operating at 10 Gb/s are required for a 10-Gb/s direct-detection optical receiver. The best performance to date using Si bipolar technology is a 10-GHz bandwidth preamplifier or a 3.6-GHz bandwidth gain-controllable amplifier. A preamplifier and gain-controllable amplifier with a bandwidth exceeding 10 GHz, and decision circuits operating at 10 Gb/s are achieved by optimized high-speed silicon bipolar circuit blocks, including a dual feedback loop, peaking circuit, and impedance matched buffer to achieve a 11.2-GHz bandwidth with 53-dB Omega transimpedance gain. The gain-controllable amplifier uses a current-dividing gain-control and emitter peaking circuit and has 11.4-GHz bandwidth with 20-dB variable gain.<<ETX>>

2.8 Gb/s 176 mW byte-interleaved and 3.0 Gb/s 118 mW bit-interleaved 8:1 multiplexers

2.8 Gbps/176 mW byte-interleaved and 3.0 Gbps/l18 mW bit-interleaved 8:1 multiplexers use 0.15 /spl mu/m CMOS technology. A byte-interleaving scheme divides input-registers into two symmetrical matrices to realize a high-density layout. Both chips have the same 8:1 time-division multiplexing core with a static shift-register architecture. The critical path delay is reduced by introducing dual-outputs D-FFs for the shift-registers. Bit-clock and byte-clock are precisely distributed to maximize speed. Direct interface with ECL circuits uses a negative supply of -2 V (VTT) and high-speed I/O buffers.

A self-aligned SiGe base bipolar technology using cold wall UHV/CVD and its application to optical communication ICs

A self-aligned SiGe base bipolar technology and its application to optical communication ICs are presented. Using cold wall ultra-high vacuum (UHV)/CVD technology, a self-aligned selective SiGe/Si epitaxial growth can be realized for the overhanging structure of the base electrode polysilicon. This is a novel self-aligned bipolar transistor, which we call a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor. The maximum cut-off frequency f/sub T/ of 60 GHz and the maximum frequency of operation f/sub max/ of 50 GHz have been obtained. This technology has been applied to optical communication ICs. A receiver and a transmitter ICs fabricated on a silicon on insulator (SOI) substrate stably operate at up to 20 Gb/s.

Pseudomorphic 2DEG FET IC's for 10 Gb/s optical communication systems with external optical modulation

An optical modulator driver IC and a preamplifier IC for 10 Gb/s optical communication systems are developed using AlGaAs/InGaAs/GaAs pseudomorphic two-dimensional electron gas (2DEG) FETs with a gate length of 0.35 mu m. The optical modulator driver IC operates at a data rate up to 10 Gb/s with an output voltage swing of more than 4 V/sub p-p/. The bandwidth for the amplifier IC is 13.0 GHZ with ab 47 dB- Omega transimpedance gain. In addition, optical transmission experiments with external optical modulation using these ICs have successfully been carried out at 10 Gb/s. >

SiGe bipolar ICs for 20 Gb/s optical transmitter

SiGe bipolar ICs, a selector, a multiplier and a D-type flip-flop, have been developed for a 20 Gb/s optical transmitter by using a self-aligned SiGe base bipolar transistor with bonded SOI technology. In the selector IC and the multiplier IC, an internal high speed clock buffer circuit accomplishes stable operation under a single clock input condition.