Takasuke Hashimoto

A selective epitaxial SiGe/Si planar photodetector for Si-based OEIC's

A P-i-N SiGe/Si superlattice photodetector with a planar structure has been developed for Si-based opto-electronic integrated circuits. To make the planar structure, a novel SiGe/Si selective epitaxial growth technology which uses cold wall ultrahigh-vacuum/chemical vapor deposition has been newly developed. The P-i-N planar SiGe/Si photodetector has an undoped 30-/spl Aring/ Si/sub 0.9/Ge/sub 0.1//320-/spl Aring/ Si, 30 periods, superlattice absorption layer, a 0.1-/spl mu/m P-Si buffer layer, and a 0.2-/spl mu/m P/sup +/-Si contact layer on a bonded silicon-on-insulator (/spl eta//sub ext/). The bonded SOI is used to increase the external quantum efficiency (/spl eta//sub ext/) of the photodetector. Moreover, a 63-/spl mu/m deep/128-/spl mu/m wide trench, to achieve simple and stable coupling of an optical fiber to the photodetector, is formed in the silicon chip. The P-i-N planar photodetector exhibits a high /spl eta//sub ext/ of 25-29% with a low dark current of 0.5 pA//spl mu/m/sup 2/ and a high-frequency photo response of 10.5 GHz at /spl lambda/=0.98 /spl mu/m.

A super self-aligned selectively grown SiGe base (SSSB) bipolar transistor fabricated by cold-wall type UHV/CVD technology

A novel selective epitaxial growth (SEG) technology for fabricating the intrinsic SiGe-base layer of a double poly-Si self-aligned bipolar transistor has been developed. Selectively grown Si and SiGe-alloy layers were obtained by using Si/sub 2/H/sub 6/+GeH/sub 4/+Cl/sub 2/+B/sub 2/H/sub 6/ gas system using cold-wall ultra-high vacuum (UHV)/CVD. We have optimized the growth conditions so that Si or SiGe grows selectively against Si/sub 3/N/sub 4/ both on single crystalline Si and on poly-Si of a structure consisting of a poly-Si layer overhanging the single crystalline Si substrate. The selective growth is maintained until the growth from the bottom Si and the top poly-Si coalesce. This selective growth permits a novel emitter-base self-aligned transistor which we call a super self-aligned selectively grown SiGe base (SSSB) HBT. >

A 60-GHz f/sub T/ super self-aligned selectively grown SiGe-base (SSSB) bipolar transistor with trench isolation fabricated on SOI substrate and its application to 20-Gb/s optical transmitter ICs

A 60-GHz cutoff frequency (f/sub T/) super self-aligned selectively grown SiGe-base (SSSB) bipolar technology is developed. It is applied to 20-Gb/s optical fiber transmitter ICs. Self-aligned bipolar transistors mutually isolated by using a BPSG-filled trench were fabricated on a bond-and-etchback silicon-on-insulator (SOI) substrate to reduce the collector-substrate capacitance C/sub CS/. The SiGe base was prepared by selective epitaxial growth (SEG) technology. A 0.4-/spl mu/m wide emitter was used to reduce the junction capacitances. The maximum cutoff frequency f/sub T/ and the maximum frequency of oscillation f/sub max/ were 60 and 51 GHz, respectively. By using this technology, Si-ICs for an optical transmitter system were made, such as a selector (a multiplexer without input and output retiming D-type flip-flops (D-F/Fs)), a multiplier, and a D-F/F. An internal high-speed clock buffer circuit achieves stable operation under a single clock input condition in the selector and the multiplier ICs. Their stable operation was confirmed up to 20 Gb/s. The selector IC for data multiplexing operates at over 30 Gb/s.

Sub-20 ps ECL circuits with high-performance super self-aligned selectively grown SiGe base (SSSB) bipolar transistors

This paper describes a high maximum frequency of oscillation f/sub max/ self-aligned SiGe-base bipolar transistor technology, based on a self-aligned selective epitaxial growth (SEG) technology including graded Ge profile in an intrinsic base and link-base engineering using a borosilicate glass (BSG) sidewall structure. The transistor is a new self-aligned transistor, which we call a Super Self-aligned Selectively grown SiGe Base (SSSB) bipolar transistor. The 1st step of the annealing (800/spl deg/C, 10 min) was performed for the diffusion of boron from the BSG film, before the deposition of an emitter polysilicon film. The 2nd step of the annealing (950/spl deg/C, 10 sec) of emitter drive-in was carried out, which enabled us to obtain sufficient current gain using in-situ phosphorus doped polysilicon as an emitter electrode. Sheet resistance for a link-region more than one order lower than that of the epitaxial intrinsic base was obtained after heat treatment. Base profile (boron and Ge) design, and the 2-step annealing technique have realized cut-off frequency f/sub T/ of 51 GHz and f/sub max/ of 50 GHz. ECL circuits of 19-psec gate delay have been achieved. >

Si-analog IC's for 20 Gb/s optical receiver

This paper describes two kinds of Si-analog ICs, a preamplifier IC and a decision IC consisting of a gain-controllable amplifier and a D-type flip flop (D-F/F) for a 20 Gb/s optical receiver. A 20 Gb/s optical receiver for the generation beyond 10 Gb/s has been fabricated in hybrid circuit technology. However, the development of high-speed analog ICs operating at 20 Gb/s, making possible reduced system size, is indispensable for stable system operation in practical application. >

0.1 /spl mu/m delta-doped MOSFET using post low-energy implanting selective epitaxy

Delta-doped NMOSFETs with 0.1 /spl mu/m gate length were fabricated by using Post Low-energy Implanting Selective Epitaxy (PLISE). Non-doped epitaxial channel layers were grown by UHV-CVD after BF/sub 2/ ion implanting at 10 keV. The delta-shaped doping configuration suppresses short-channel effects and reduces the junction capacitance. It allows the switching speed one and a half times faster than conventional approaches. The minimum gate delay is 7.2 ps at 2.5 V for an NMOS ring oscillator with a 10 /spl mu/m gate width and a 1 K/spl Omega/ load.<<ETX>>

A 2.4 Gb/s receiver and a 1:16 demultiplexer in one chip using a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor

This paper reports a 2.4 Gb/s optical terminal IC that integrates high-speed analog and digital circuits for future optical networks using 60-GHz f/sub T/ self-aligned silicon-germanium (SiGe)-alloy base bipolar transistors. The selective epitaxial growth (SEG) SiGe base was formed by using cold-wall ultra-high vacuum (UHV)/CVD technology. Boron concentration reduction at the SiGe epitaxial layer/Si-substrate interface by using a new treatment prior to SEG leads to electrical characteristics with less dependence on bias voltage. The IC consists of a receiver (a preamplifier, an automatic gain control (AGC) amplifier, a phase-locked loop (PLL), and a D-type flip-flop (D-F/F)), and a 1:16 demultiplexer (DMUX). An input offset control circuit is included in the AGC amplifier for wide dynamic range. Trench isolation and silicon-on-insulator (SOI) technologies are introduced to reduce crosstalk between the amplifiers and the PLL. Power consumptions are 0.6 W at -5.2 V for the analog part and 0.45 W at -3.3 V for the digital part, which does not include the ECL output buffers.

A SiGe single-chip 3.3 V receiver IC for 10 Gb/s optical communication systems

A SiGe single-chip 3.3 V receiver IC for 10 Gb/s optical communication systems integrates a transimpedance preamplifier, a limiting amplifier with a reference voltage generator, and a clock and data recovery (CDR) circuit with a phase-locked loop (PLL). For this IC, phase-comparison automatically adjusts the clock phase to the optimum point for data regeneration in the CDR circuit. The receiver IC uses a SiGe bipolar transistor with 60 GHz cutoff frequency. It operates at 10 Gb/s with 660 mW power consumption at 3.3 V.

A selective epitaxial SiGe/Si planar photodetector for Si-based OEICs

This paper reports, for the first time, a P-i-N SiGe/Si superlattice photodetector with a planar structure for Si-based OEICs (Opto-Electronic Integrated Circuits). To make the planar structure, a novel SiGe/Si selective epitaxial growth technology by a cold wall UHV (Ultra-High-Vacuum)/CVD is newly developed. The P-i-N planar SiGe/Si photodetector exhibits a high external quantum efficiency (/spl eta//sub ext/) of 25%-29% with a low dark current of 0.5 pA//spl mu/m/sup 2/ and responds up to 10 Gbit/s at /spl lambda/=0.98 /spl mu/m.

A self-aligned SiGe base bipolar technology using cold wall UHV/CVD and its application to optical communication ICs

A self-aligned SiGe base bipolar technology and its application to optical communication ICs are presented. Using cold wall ultra-high vacuum (UHV)/CVD technology, a self-aligned selective SiGe/Si epitaxial growth can be realized for the overhanging structure of the base electrode polysilicon. This is a novel self-aligned bipolar transistor, which we call a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor. The maximum cut-off frequency f/sub T/ of 60 GHz and the maximum frequency of operation f/sub max/ of 50 GHz have been obtained. This technology has been applied to optical communication ICs. A receiver and a transmitter ICs fabricated on a silicon on insulator (SOI) substrate stably operate at up to 20 Gb/s.