Thammavarapu R. N. Rao

Decoding algebraic-geometric codes up to the designed minimum distance

A simple decoding procedure for algebraic-geometric codes C/sub Omega /(D,G) is presented. This decoding procedure is a generalization of Petersons decoding procedure for the BCH codes. It can be used to correct any ((d*-1)/2) or fewer errors with complexity O(n/sup 3/), where d* is the designed minimum distance of the algebraic-geometric code and n is the codelength. >

An SFS Berger check prediction ALU and its application to self-checking processor designs

A strongly fault secure (SFS) ALU design based on the Berger check prediction (BCP) technique is presented. The fault and error models of a large class of VLSI ALU designs are discussed. The proposed design is proved to be fault-secure and self-testing with respect to any single fault in the ALU part. The proposed BCP ALU is proved to be SFS with any design of BCP circuit. Consequently, a self-checking processor whose data path is encoded entirely in a Berger code can be achieved. An efficient self-checking processor can then be designed. >

Improved geometric Goppa codes. I. Basic theory

In this paper, we present a construction of improved geometric Goppa codes which, for the case of r<2g, are often more efficient than the current geometric Goppa codes derived from some varieties, which include algebraic curves, hyperplanes, surfaces, and other varieties. For the special case of a plane in a three-dimensional projective space, the improved geometric Goppa codes are reduced to linear multilevel codes. For these improved geometric Goppa codes, a designed minimum distance can be easily determined and a decoding procedure which corrects up to half the designed minimum distance is also given.

Private-key algebraic-code encryptions

An approach to private-key cryptosystems is proposed which allows use of very simple codes of distance >

Private-key algebraic-coded cryptosystems

Public-key cryptosystems using very large distance algebraic codes have been studied previously. Private-key cryptosystems using simpler codes have also been subject of some study recently. This paper proposes a new approach to the private-key cryptosystems which allows use of very simple codes such as distance 3 and 4 Hamming codes.This new approach gives not only very efficient encoding/decoding and very high information rates but also appears to be secure even under chosenplaintext attacks.

Biresidue Error-Correcting Codes for Computer Arithmetic

In an earlier paper [11] a scheme for detecting errors in ADD, COMPLEMENT, SHIFT, and ROTATE operations using a residue check circuitry was presented. A scheme for error location and correction in those operations is derived by a suitable application of a code called biresidue arithmetic code described here. Any single error position can be located and also corrected by use of two residue checkers which work separately and in parallel with the arithmetic unit. The estimated cost of redundancy is approximately the same as that required for duplication of the arithmetic unit.

Concurrent error detection in arithmetic and logical operations using Berger codes

A novel approach to designing concurrent-error-detecting arithmetic and logic units using Berger code is presented. Several theorems are developed on Berger check predictions for arithmetic and logical operations. Specifically, the Berger check prediction is proposed for additions and subtractions with unsigned numbers as well as signed numbers. Berger check prediction for 16 logical operations and shift operations, multiplication, and division are given. The proposed scheme may provide a considerable saving in the hardware logic (or chip area) in implementing a self-checking arithmetic logic unit (ALU) and may ultimately make feasible a single-chip self-checking microprocessor or reduced-instruction-set-computer (RISC) design.<<ETX>>

Berger check prediction for array multipliers and array dividers

The authors present closed-form check-predicting equations for deriving Berger checks (J.M. Berger, 1961) for array multipliers and array dividers, respectively. Brauns array multipliers and Guilds array dividers are examined. Example check circuits are also presented. >

Binary Logic for Residue Arithmetic Using Magnitude Index

We consider a residue number system using n pairwise relatively prime moduli m1,⋯,mnto represent any integer X in the range M/ 2≤X>M/2, when M = ∏mi. The moduli miare chosen to be of the 2-1 type, in order that the residue arithmetic can be implemented by means of binary registers and binary logic. Further, for each residue number X, a magnitude index Pxis maintained for all arithmetic operations. We investigate the properties of such a system and derive the addition, subtraction, multiplication, sign determination, and overflow detection algorithms. The proposed organization is found to improve the operation times for sign detection and overflow detection operations, while rendering multiplication to be a difficult operation.

Use of Error Correcting Codes on Memory Words for Improved Reliability

Application of error correcting coding is often employed to improve system operation and reliability. By means of suitable reliability models and simple analysis, the effect of error correcting coding of memory words on the overall reliability of the system is discussed. Introduction of error correcting facilities will generally have three significant effects on the system: 1) increased hardware, which is also subject to failures and hence tends to lower reliability; 2) the systems ability to function in the presence of a certain class of failures; and 3) quicker detection of errors, which also means an improved repair rate. To illustrate the extent to which the above three factors govern the reliability improvement due to coding, three types of systems are considered. These systems use the same basic processor and memory units but differ in their structure and complexity. Other factors besides the three above which control the reliability improvement due to coding are the system structure and the relative sizes of processor and memory hardware.