Jien-Chung Lo

A fast binary adder with conditional carry generation

This paper presents a fast binary adder in static CMOS realization. While the carry derivation is similar to that in a conditional-sum adder, the proposed adder is also similar to that of a spanning tree carry lookahead adder in the sense that only selected carry bits are generated and the sum bits are produced by carry-select adders. In a 1.2 /spl mu/m static CMOS realization, the proposed adder adds two 32-bit operands in 3.28 ns. This delay is measured from the assertion of the input to the arrival of the slowest sum bit.

Probability to achieve TSC goal

We propose a probabilistic measure for self-checking (SC) circuits that is analogous to reliability of fault-tolerant systems. This measure is defined as the probability to achieve totally self-checking (TSC) goal at the lth cycle: TSCG(t). TSCG provides insight to the worst case dynamic behavior of SC circuits with respect to the application environment and component failure rates. TSCG surpasses the TSC definitions in determining the applicability of a circuit in a given application environment. An SC circuit achieves TSC goal when no erroneous information or data is propagated beyond the boundary of this circuit. TSCG is therefore the probability that this fault confinement mechanism is intact. The SC properties are obtained through adding hardware redundancy to the original digital design, which means that an SC circuit has a higher failure rate than the original circuit. Further, there are tradeoffs between the level of hardware redundancy, the reliability, and the TSCG. We give several examples to clearly demonstrate these tradeoffs for different design environments. We emphasize that the TSCG is intended to provide a mean of dynamic error handling performance evaluation of SC designs. The TSC definitions and alike are still intact, since a cost-effective SC circuit must begin with a TSC circuit. The TSCG gives confidence in the use of cost-efficient error control codes and/or reduction in error handling capability. Analogous to reliability, the TSCG can be used in product specifications. This is a crucial step toward the practical applications of TSC or CED circuits.

On-chip jitter measurement for phase locked loops

In this paper, we propose an efficient on-chip method for the direct measurement of jitter in phase locked loops (PLLs). The jitter is first detected as the phase difference in the form of pulses with duration in the range of pico-seconds. A combination of a modified charge pump and a binary counter can then record the number that represents the jitter measurement. This is the first attempt to directly measure the jitter of PLLs on-chip via analog testing circuit, but with digital output. The proposed testing circuit is only about 20% of the PLL under test. The proposed on-chip jitter measurement circuit is a central part of built-in self-test for many embedded applications in SOCs.

Analysis of a BICS-only concurrent error detection method

We propose a BICS-only method for concurrent error detection (CED) where a built-in current sensor (BICS) is solely responsible for detecting faults and errors. Due to the wide applicability of the BICS, this approach can be applied directly to combinational circuits, sequential circuits, and even some analog circuits. A dependability model was developed to study the effectiveness of the proposed BICS-only method. The unsafe probability of the BICS-only design is sensitive to both fault coverage and testability of the BICS. When used in a duplicated CED system for fault masking, the system reliability is sensitive to the fault coverage, but not to the testability of the BICS. Next, we show that a dramatic increase in unsafe probability is possible if the BICS cannot perform detection at every system clock cycle. A higher testability for BICS will, contrary to our intuition, make the unsafe probability higher. For duplicated CED applications, the reliability will be even lower than that of a nonredundant system. Therefore, the design criteria for BICS in the BICS-only method, in the order of importance, are: operating speed, fault coverage, and testability.

Delay chain based programmable jitter generator

In this paper, we presents a programmable jitter generator. Different from the traditional jitter generator that uses the analog phase modulation (PM) technique to generate only non-Gaussian distributed jitter components, the proposed jitter generator uses digital techniques. It consists of a voltage controlled delay chain, jitter control block, and some basic digital components. It can generate not only the non-Gaussian distributed jitter component, but also the Gaussiandistributed jitter component. In addition, almost all jitter characteristics are controllable. This jitter generator can be used in jitter tolerance test and jitter transfer function measurement. A Xilinx XC4010 FPGA chip is used to validate this design.

Reliable logic circuits with byte error control codes-a feasibility study

This paper addresses the relations between logic circuit synthesis, error model and error control codes so that the efficient reliable logic circuits can be obtained. We propose that single fault masking capability of a random logic circuit can be obtained by encoding its outputs in a byte error correcting code; this is equivalent to that of the triple module redundancy (TMR) technique. Similarly, byte error detecting code can be used to provide an equivalence of duplication. In this paper, we address the problems and issues related to the realization of byte-organized configuration where the byte error control codes can be applied. Some MCNC benchmark circuits are used as examples to demonstrate the feasibility of the proposed concept.

A probabilistic measurement for totally self-checking circuits

The authors propose a probabilistic measurement for totally self-checking (TSC) circuits. This measurement is analogous to reliability of fault-tolerant systems and is defined as the probability of achieving TSC goal (PATG). PATG surpasses the TSC definitions in determining the applicability of a circuit in a given application environment. For example, it is shown that an embedded TSC two-rail checker with two out of its four code word inputs unavailable gains a higher PATG than that in the ideal case. It is also demonstrated that the extension of PATG concept to strongly fault-secure (SFS) circuits and strongly code disjoint (SCD) checkers. The PATG can be used in product specification, analogous to reliability, and can give precise behavioral description on fault/error handling performance of TSC circuits. This is a crucial step toward the practical applications of TSC or CED circuits.

Single fault masking logic designs with error correcting codes

Triple modular redundancy (TMR) has been the most popular method in reliable logic designs due to a single fault masking capability. However, the reliability of a TMR design can be improved only by enhancing the reliabilities of the components. This paper examines the use of error correcting codes in reliable logic design. The goal is to provide an equivalent single fault masking capability as that of TMR scheme. Further, by reducing the level of hardware redundancy, a higher reliability can be achieved. Design examples are given to illustrate the key issues in single fault masking logic designs with error correcting codes. Reliabilities of different single fault masking carry lookahead adder designs are also examined.

An indirect current sensing technique for IDDQ and IDDT tests

An indirect current sensing technique for <i>I<inf>DDQ</inf></i> and <i>I<inf>DDT</inf></i> tests is proposed in this paper. This is accomplished by utilizing the pervasive on-chip voltage regulators and thus have little or no impact on CUTs design and its performance. We demonstrate that the proposed technique can be applied to both <i>I<inf>DDQ</inf></i> and <i>I<inf>DDT</inf></i> tests. Experiments were successfully conducted in SPICE simulations assuming the TSMC 0.18μm CMOS technology.

Equivalent IDDQ Tests for Systems with Regulated Power Supply

This paper presents an equivalent current sensing technique for the applications o tests. This is accomplished by monitoring the operations of existing on-chip voltage regulators, which indirectly provides the IDDQ information. Equivalent IDDQ information is obtained by measuring an internal voltage signal of a regulator. Then, the measured data is shifted out using the IEEE 1149.1 standard. IDDQ based test methods are used to post-process those data for screening defective circuits. Experiments were successfully conducted assuming the TSMC 0.18mum CMOS technology