Thanh T. Tran

System-on-chip choices [RISC or DSP solution]

For many years the decision between a RISC or DSP solution was relatively simple as RISCs and DSPs were never integrated on the same device. The rule used was an 80/20 rule. That is, if the greater part of the processing (i.e., 80 percent) is for data, then attempt to do the signal processing on the RISC. If the greater portion of the processing (i.e., 80 percent) is for signals, attempt to do the data processing on the DSP. But with the ability to integrate both RISCs and DSPs onto the same piece of silicon, the choice becomes more complex. With the addition of programmable accelerators, ASIC and FPGAs also integrated on the same piece of silicon, the choices become almost impossible. The correct choice is not always based on a technical basis. The decisions truly become an optimization of flexibility, ease of use, cost, power and performance. Simply put, the winning strategy is to find a solution which has good enough performance, low enough power dissipation, and low enough price to be first to market. This strategy is referred as a P/sup 3/ strategy. This paper outlines a concept to help system designers selecting the right SOC architecture and optimizing the performance by allocating the right tasks to the right processor.

A Personal Video Recording System Using H.264 and MPEG-2 Transport Stream

This article describes a personal video recorder (PVR) system that uses H.264 for video coding and MPEG-2 transport stream as data format for simultaneous record and playback. Using H.264 provides two times longer recording time over MPEG-2 based on the same video quality. The 2004 amendment of the MPEG-2 system standard added support for the transport of none MPEG-2 AVC video data using MPEG-2 transport stream. This article discusses the overall architecture of the PVR and several key technical aspects of the implementation, including A/V capture, synchronization, storage and play-back. The implementation uses the Davinci digital video software development kit (DVSDK).

Scalable heterogeneous SoC (HeSoC) platform

The processing of multi-channel high-definition (HD) videos in real-time has imposed many challenges to researchers and engineers in finding an optimal balance between programmability and hardware efficiency. This paper introduces a scalable heterogeneous SoC (HeSoC) platform which consists of multiple-SoCs inter-connected in a mesh network where each SoC provides both DSP-like design flexibility and ASIC-like performance simultaneously. The final paper will provide detailed description on motivation and principles of mapping advanced coding tools into hardware and software modules to achieve the best coding efficiency and flexibility.

Transmission Line (TL) Effects

Transmission line (TL) effects are one of the most common causes of noise problems in high-speed DSP systems. When do traces become TLs and how do TLs affect the system performance? A rule-of-thumb is that traces become TLs when the signals on those traces have a rise-time (Tr) less than twice the propagation delay (Tp). For example, if a delay from the source to the load is 2nS, then any of the signals with a rise-time less than 4nS becomes a TL. In this case, termination is required to guarantee minimum overshoots and undershoots caused by reflections. Excessive TL reflections can cause electromagnetic interference and random logic or DSP false-triggering. As a result of these effects, the design may fail to get the FCC certification or to fully function under all operating conditions such as at high temperatures or over-voltage conditions.

Data Converter Overview

This chapter provides an overview of analog-to-digital and digital-toanalog converters and their applications to audio and video systems design. There are many factors affecting the performance of the converters and these can be minimized if designers understand the converter’s sampling techniques and quantization noise, the necessity of having input and output filters and the proper system design and layout.

Analog Filter Design

This chapter presents passive and active filter topologies and design techniques, including practical design examples and system simulations. In DSP systems, there are analog filters required for signal conditioning and limiting the bandwidth before sampling. To design these filters, designers need to be knowledgeable of operational amplifiers, DC biasing circuits, AC coupling techniques and traditional passive components like inductors, capacitors and resistors.

Power Supply Decoupling

The number one root cause of system related problems is due to inadequate power supply decoupling around the DSP and or other surrounding circuits such as DDR, clocks, analog-to-digital and digital-to-analog converters etc. The most challenging task for designers is to determine the best decoupling techniques to achieve low noise and high performance. In general, component manufactures provide a conservative recommendation for power supply decoupling, but in many cases, it is not practical to follow this recommendation because of PCB space availability, power consumption, EMI or safety requirements. Also, component manufactures always provide development platforms for designers to evaluate and these platforms typically are a lot larger than the actual design and are not required to be FCC certified, so copying what was done on the development platform is not a guaranteed that the design will be successful. This chapter will discuss three important topics for designers: 1. a general rule-ofthumb decoupling method, 2. an analytic decoupling method and 3. how to make design tradeoffs to achieve the best noise performance possible.

Memory Sub-System Design Considerations

The most critical bus in a DSP system today is the memory bus where a large amount of ultra high speed data is being transferred from the DSP to the physical memory devices and vice versa. The data on this bus are switching very fast. The rise and fall times of the data, memory clocks, control signals are approaching sub-nanosecond range. These fast transients generate noise, radiation, power supply droops, signal integrity, and memory timing issues. This chapter covers memory sub-system design techniques to minimize the effects of the high speed data propagating.

Electromagnetic Interference (EMI)

Radiated emissions in high-speed DSP systems are caused by fastswitching currents and voltages propagating through printed circuit board traces. As DSP speed increases, printed circuit board traces are becoming more effective antennas, and these antennas are radiating unwanted energies that interfere with other circuitry and with other systems located nearby. This section outlines different ways to design for low EMI and find the root cause of EMI problems when they occur. It only covers the electrical design aspects of EMI even though shielding, cabling and other mechanical fixes can also be used to help reduce the emissions below the maximum allowable limits. In general, mechanical solutions are very expensive for high volume designs. Even worse, the mechanical solutions may have to change when the DSP speed increases.

Power Supply Design Considerations

Power supply design is perhaps the most challenging aspect of the entire process of controlling noise and radiation in high-speed DSP design. This is largely because of the complexity of the dynamic load switching conditions. These include the DSP going into or out of low power modes, excessive in-rush current due to bus contention and charging decoupling capacitors, large voltage droop due to inadequate decoupling and layout, oscillations that overload the linear regulator output, and high current switching noise generated by switching voltage regulators. A clean and stable power supply design is required for all DSP systems to guarantee system stability. This chapter outlines the importance of proper power supply design and the methods to minimize unwanted noise.