Theerayod Wiangtong
Mahanakorn University of Technology
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Publication
Featured researches published by Theerayod Wiangtong.
Design Automation for Embedded Systems | 2002
Theerayod Wiangtong; Peter Y. K. Cheung; Wayne Luk
This paper compares three heuristic search algorithms: genetic algorithm (GA), simulated annealing (SA) and tabu search (TS), for hardware–software partitioning. The algorithms operate on functional blocks for designs represented as directed acyclic graphs, with the objective of minimising processing time under various hardware area constraints. Thecomparison involves a model for calculating processing time based on a non-increasing first-fit algorithm to schedule tasks, given that shared resource conflicts do not occur. The results show that TS is superior to SA and GA in terms of both search time and quality of solutions. In addition, we have implemented an intensification strategy in TS called penalty reward, which can further improve the quality of results.
international symposium on communications and information technologies | 2006
Noppadol Khaehintung; Theerayod Wiangtong; Phaophak Sirisuk
This paper describes FPGA implementation of a maximum power point tracking (MPPT) for photovoltaic (PV) applications. By slightly modifying the original algorithm, an improved variable step-size P&O algorithm is realized and efficiently implemented using a hardware description language (VHDL). Subsequently, the new MPPT algorithm integrated with a solar-powered battery charging system is implemented on the XC2C384 FPGA without external sensor unit requirement. Experimental results with a commercial PV array show that the proposed algorithm outperforms the conventional controller in terms of tracking speed and mitigation of fluctuation output power in steady state operation. The overall system efficiency is well above 96%
IEEE Signal Processing Magazine | 2005
Theerayod Wiangtong; Peter Y. K. Cheung; Wayne Luk
This article presents a systematic approach to hardware/software codesign targeting data-intensive applications. It focuses on the application processes that can be represented in directed acrylic graphs (DAGs) and use a synchronous dataflow (SDF) model, the popular form of dataflow employed in DSP systems when running the process. The codesign system is based on the ultrasonic reconfigurable platform, a system designed jointly at Imperial College and the SONY Broadcast Laboratory. This system is modeled as a loosely coupled structure consisting of a single instruction processor and multiple reconfigurable hardware elements. The paper also introduces and demonstrates a task-based hardware/software codesign environment specialized for real-time video applications. Both the automated partitioning and scheduling environment and the task manager program help to provide a fast robust for supporting demanding applications in the codesign system.
international symposium on circuits and systems | 2000
Theerayod Wiangtong; Worranart Sangchai; Pichit Lumyong
This paper presents an application of an ALTERA FPGA Device, in the FLEX1OK family, producing pulse width modulation (PWM) signals with the vector modulation technique for an IGBT inverter. Using a single FPGA chip for the practical implementation of the modulator, rather than a system consisting of microprocessor and external memory, has many advantages including less use of power and space, short design time, greater speed and reliability. The designed circuit can generate PWM signals at many different frequencies, and also, the input values used to adjust output signal may be obtained through either a 4/spl times/4 keypad or microprocessor port.
field-programmable custom computing machines | 2002
Theerayod Wiangtong; Peter Y. K. Cheung; Wayne Luk
This paper presents tabu search (TS) method with intensification strategy for hardware-software partitioning. The algorithm operates on functional blocks for designs represented as directed acyclic graphs (DAG), with the objective of minimising processing time under various hardware area constraints. Results are compared to two other heuristic search algorithms: genetic algorithm (GA) and simulated annealing (SA). The comparison involves a scheduling model based on list scheduling for calculating processing time used as a system cost, assuming that shared resource conflicts do not occur. The results show that TS, which rarely appears for solving this kind of problem, is superior to SA and GA in terms of both search time and the quality of solutions. In addition, we have implemented intensification strategy in TS called penalty reward, which can further improve the quality of results.
field-programmable logic and applications | 2003
Theerayod Wiangtong; Peter Y. K. Cheung; Wayne Luk
To achieve a good performance when implementing applications in codesign systems, partitioning and scheduling are important steps. In this paper, a two-phase clustering algorithm is introduced as a preprocessing step to an existing hardware/software partitioning and scheduling system. This preprocessing step increases the granularity in the partition design, resulting in a higher degree of parallelism and a better mapping to the reconfigurable resource. This cluster-driven approach shows improvements in both the makespan of the implementation, and the CPU runtime.
international conference on electrical engineering/electronics, computer, telecommunications and information technology | 2009
Veerachai Malyavej; Peerapong Torteeka; Siripong Wongkharn; Theerayod Wiangtong
Pose estimation is one of the most important part of guidance systems in unmanned vehicles. In this paper, we consider the problem of pose estimation of unmanned ground vehicle (UGV) equipped with a global positioning system (GPS), an odometer and an electronic compass. The unscented Kalman filter (UKF) is used to fuse the information from those sensors. To improve the accuracy and robustness, we also propose the method to calibrate the output of electronic compass. The experimental results strongly confirm the benefit of our simple algorithm even during GPS outage in some short period of time.
international symposium on circuits and systems | 2003
Theerayod Wiangtong; Peter Y. K. Cheung; Wayne Luk
This paper presents a new approach for modeling hardware and software tasks in codesign system. The model has the advantage that the hardware tasks are structured in a way that is compatible with the software tasks. As a result, both hardware and software tasks can be managed in a uniform manner using a single task manager. A hardware/software partitioning and schedule algorithm is developed to automatically map the tasks to the codesign resources to minimize the processing time (makespan). The practicality of our approach is demonstrated with an implementation of dummy tasks for an existing reconfigurable computer, the UltraSONIC. The results show that our approach is promising for a real application.
field-programmable logic and applications | 2003
Theerayod Wiangtong; Peter Y. K. Cheung; Wayne Luk
This paper presents a codesign environment for the UltraSONIC reconfigurable computing platform which is designed specifically for real-time video applications. A codesign environment with automatic partitioning and scheduling between a host microprocessor and a number of reconfigurable processors is described. A unified runtime environment for both hardware and software tasks under the control of a task manager is proposed. The practicality of our system is demonstrated with an FFT application.
applied reconfigurable computing | 2009
Sirisak Leephokhanon; Theerayod Wiangtong
This paper presents a multi-camera system where reconfigurable hardware and video codec are used to assist real-time video processing. Video inputs from all analog cameras are decoded and processed by FPGA to accelerate overall processing time. Two applications including multiple-object tracking and motion capturing are implemented in this system to verify real-time capability. In multiple-object tracking, video images are rearranged and combined into a single image that profits the tracking algorithm called multiple-CAMshift running in software. In motion capturing, every frame from all cameras, located in different angles, is processed to find the coordinates of 11 reference color-objects. Results are sent to a computer for constructing 3-D image in real-time.