Themistoklis Haniotakis

A security protocol for sensor networks

We present in this paper a new security protocol especially suited for sensor networks. This protocol uses a novel encryption method for secure message transmission. We present the details of this encryption scheme along with experimental results performed on a network simulator.

A Methodology for Transistor-Efficient Supergate Design

The number of transistors required for the implementation of a logic function is a fundamental consideration in digital VLSI design. While the determination of a series-parallel implementation can be straightforward once a simplified Boolean expression of the function is available, this may not be an optimum solution. In this paper, a methodology is developed for minimizing the number of transistors that starts from a sum-of-products expression and utilizes non-series-parallel structures. Experimental results demonstrate the efficiency of the approach

A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs

In this paper a new circuit for concurrent soft and timing error detection in CMOS ICs is presented. The circuit is based on current mode sense amplifier topologies to provide fast error detection times. After an error has been detected it can be corrected by using a retry cycle.

A Design Technique for Energy Reduction in NORA CMOS Logic

In this work, a design technique to reduce the energy consumption in NO RAce (NORA) circuits is presented. The technique is based on a unidirectional switch topology combined with a new clocking scheme permitting both charge recycling between circuit nodes and elimination of the short circuit current. Calculations proved that energy savings higher than 20% can be achieved. Simulation results from NORA designs in a 0.18-mum CMOS technology are presented to demonstrate the effectiveness of the proposed technique to achieve both energy and energy-delay product reduction

Transistor-Level Optimization of Supergates

The chip area and delay in digital VLSI design depends on the number of transistors that are used for the logic gates involved. While the determination of a series-parallel implementation can be straightforward once a simplified expression of the function is available, this may not be an optimum solution. In the current paper an improved approach for determining a satisfactory solution for complex gates is presented. Experimental results demonstrate the efficiency of the approach

Delay Analysis for an N-Input Current Mode Threshold Logic Gate

A recent approach is capable of identifying threshold logic functions with as many as fifty inputs with small integer weights on the inputs. An analytical method is presented for selecting optimum sensor sizes. This allows us to design large threshold functions with delay much less than a network of CMOS gates. Exhaustive SPICE simulations show that implemented TLGs by the proposed approach consistently exhibit behavior very close to the optimal.

A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism

High reliability requirements in many modern applications make soft errors an extremely important design aspect and pose new challenges in nanometer technologies. In addition, timing faults that may escape fabrication tests become a real concern in high complexity, high frequency designs. To confront this situation, a concurrent error detection and correction circuit and technique are presented in this work. Their application in pipeline architectures is analyzed and the pipeline error recovery mechanism is illustrated. The proposed scheme is characterized by low silicon area requirements, compared to earlier approaches, and the need of only a single clock cycle for pipeline recovery.

New test pattern generation units for NPSF oriented memory built-in self test

In this paper we present the design of deterministic test pattern generation (TPG) units which can be exploited in a built-in self-test (BIST) scheme for memory neighborhood pattern sensitive fault (NPSF) testing. The proposed TPG units generate the required Eulerian sequence of test patterns for memory type-1 NPSF testing.

An embedded IDDQ testing circuit and technique

Quiescent current (IDDQ) testing is a valuable defect detection technique in CMOS ICs. However, its application in very deep submicron technologies is susceptible to the increased transistor leakage current. In this paper, an IDDQ testing technique and circuit are presented based on the background current compensation concept. This technique is independent from process and temperature variations and first experimental results from a fabricated circuit show that it is able to extend the viability of IDDQ testing in future nanometer technologies.

A new scheme for effective I/sub DDQ/ testing in deep submicron

I/sub DDQ/, testing has become a widely accepted defect detection technique in CMOS ICs. However its effectiveness in deep submicron is threatened by the increased transistor sub-threshold leakage current. In this paper a new l/sub DDQ/ testing scheme is proposed based on the use of a compensation circuit. The compensation circuit is used to eliminate, during testing, normal leakage current from the sensing node of the circuit under test so that already known [in the open literature] I/sub DDQ/ sensing techniques can be applied in deep submicron.