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Theodore Curt White

Unisys

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Featured researches published by Theodore Curt White.

Archive | 1993

Dual bus communication system connecting multiple processors to multiple I/O subsystems having a plurality of I/O devices with varying transfer speeds

Jayesh V. Sheth; Craig Weaver Harris; Theodore Curt White; Kha Nguyen; Chung W. Wong; Richard A. Cowgill

Archive | 1995

Configurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memories

Dan T. Tran; Paul B. Ricci; Jayesh V. Sheth; Theodore Curt White; Richard A. Cowgill

Archive | 1995

Cache controller utilizing a state machine for controlling invalidations in a network with dual system busses

Theodore Curt White; Jayesh V. Sheth

Archive | 1996

Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address

Theodore Curt White; Jayesh V. Sheth; Kha Nguyen; Dan Trong Tran

Archive | 1993

Interbus interface module

Theodore Curt White; Chung W. Wong; Kha Nguyen; Jayesh V. Sheth; Craig Weaver Harris

Archive | 1997

Dual bus network cache controller system having rapid invalidation cycles and reduced latency for cache access

Theodore Curt White; Javesh Vrajlal Sheth

Archive | 1997

Dual bus system with multiple processors having data coherency maintenance

Dan Trong Tran; Paul B. Ricci; Jayesh V. Sheth; Theodore Curt White; Richard A. Cowgill

Archive | 1993

Varying wait interval retry apparatus and method for preventing bus lockout

Theodore Curt White; Jayesh V. Sheth; Paul B. Ricci; Dan T. Tran

Archive | 1996

High speed two-port interface unit where read commands suspend partially executed write commands

Kha Nguyen; Theodore Curt White; Bruce Edward Moolenaar

Archive | 1996

Dual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queue

Theodore Curt White; Jayesh V. Sheth

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Jayesh V. Sheth

Unisys

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Kha Nguyen

Unisys

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Paul B. Ricci

Unisys

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Dan T. Tran

Unisys

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Richard A. Cowgill

Unisys

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Chung W. Wong

Unisys

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Craig Weaver Harris

Unisys

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Dan Trong Tran

Unisys

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Bruce Edward Moolenaar

Unisys

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Javesh Vrajlal Sheth

Unisys

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