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Paul B. Ricci

Unisys

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Publication

Featured researches published by Paul B. Ricci.

Archive | 1995

Configurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memories

Dan T. Tran; Paul B. Ricci; Jayesh V. Sheth; Theodore Curt White; Richard A. Cowgill

Archive | 1993

Cache memory system with fault tolerance having concurrently operational cache controllers processing disjoint groups of memory

David M. Kalish; Saul Barajas; Paul B. Ricci

Archive | 1992

Dual bus interface transfer system for central processing module

Wayne C. Datwyler; Paul B. Ricci

Archive | 1997

Dual bus system with multiple processors having data coherency maintenance

Dan Trong Tran; Paul B. Ricci; Jayesh V. Sheth; Theodore Curt White; Richard A. Cowgill

Archive | 1993

Varying wait interval retry apparatus and method for preventing bus lockout

Theodore Curt White; Jayesh V. Sheth; Paul B. Ricci; Dan T. Tran

Archive | 1992

Transmission logic apparatus for dual bus network

Wayne C. Datwyler; Paul B. Ricci

Archive | 1992

Translator system for message transfers between digital units operating on different message protocols and different clock rates

Wayne C. Datwyler; Paul B. Ricci

Archive | 1992

Programmable timing logic system for dual bus interface

Wayne C. Datwyler; Paul B. Ricci

Archive | 1992

Receiving control logic system for dual bus network

Wayne C. Datwyler; Paul B. Ricci

Archive | 1993

Inhibit write apparatus and method for preventing bus lockout

Theodore Curt White; Jayesh V. Sheth; Dan T. Tran; Paul B. Ricci

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Wayne C. Datwyler

Unisys

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Jayesh V. Sheth

Unisys

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Theodore Curt White

Unisys

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Dan T. Tran

Unisys

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David M. Kalish

Unisys

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Richard A. Cowgill

Unisys

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Saul Barajas

Unisys

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Dan Trong Tran

Unisys

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