Thomas D. Fletcher

A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor

Core and I/O clock design for the Pentium(R) 4 microprocessor is described. Two phase-locked loops generate core and I/O clocks supporting concurrent multiple frequencies. A clock distribution network with skew optimization and jitter reduction is designed to achieve low clock inaccuracies for processors at frequencies /spl ges/2 GHz for the core and /spl ges/4 GHz for the rapid execution engine. A global medium clock frequency is distributed. Local clock drivers generate pulsed or regular (nonpulsed) clocks at fast, medium, and slow frequencies. A 3.2-GB/s system bus is achieved using a dedicated I/O phase-locked loop with glitch protection and detection. Silicon speed path tools and clock debug features are designed to enable a short debug cycle.

A 0.18 /spl mu/m CMOS IA32 microprocessor with a 4 GHz integer execution unit

The processor has an execution unit with high bandwidth capability and low average instruction latency. The processor pipeline includes an Execution Trace Cache, Renamer, Scheduler, register file and execution unit. IA32 instructions are decoded when they are fetched from the L2 cache after a miss in the Execution Trace Cache. Serving as the primary instruction cache, the Execution Trace cache stores decoded instructions to remove the long delay for decoding IA32 instructions from this path, reducing the branch missprediction loop. Instruction traces follow the predicted execution path, not sequential instruction addresses. While this pipeline supplies the high bandwidth work stream, the length of this pipe contributes to instruction latency only when there is a branch miss-prediction (roughly once in 100 instructions).

Multi-GHz clocking scheme for Intel(R) Pentium(R) 4 microprocessor

This multi-GHz clock generation and distribution scheme enables the NetBurst/sup TM/ micro-architecture of Pentium(R) 4 microprocessor. A low-skew and jitter and low-power solution is achieved for three separate core and I/O bus frequencies for a total of six different clock frequencies running concurrently. A debug-friendly clocking environment provides easy observability, testing, and reconfiguration features, enabling rapid time to market.