Mark S. Milshtein

A 0.18 /spl mu/m CMOS IA32 microprocessor with a 4 GHz integer execution unit

The processor has an execution unit with high bandwidth capability and low average instruction latency. The processor pipeline includes an Execution Trace Cache, Renamer, Scheduler, register file and execution unit. IA32 instructions are decoded when they are fetched from the L2 cache after a miss in the Execution Trace Cache. Serving as the primary instruction cache, the Execution Trace cache stores decoded instructions to remove the long delay for decoding IA32 instructions from this path, reducing the branch missprediction loop. Instruction traces follow the predicted execution path, not sequential instruction addresses. While this pipeline supplies the high bandwidth work stream, the length of this pipe contributes to instruction latency only when there is a branch miss-prediction (roughly once in 100 instructions).

Self resetting logic register and incrementer

Register circuitry is described which is suitable for use with Self Resetting CMOS (SRCMOS) logic. It is level sensitive scan design (LSSD) compatible and complies with and implements the SRCMOS test modes. The register has been coupled to a novel high performance self resetting incrementer, which is based on a carry lookahead tree implemented in negative logic, and with a strobed final sum circuit. Hardware measurements are presented, showing a 900 ps 58-bit incrementer delay.

Lateral Ga/sub 0.47/In/sub 0.53/As and GaAs p-i-n photodetectors by self-aligned diffusion

Contact-self-aligned diffusion and compositional mixing has been utilized in the fabrication of lateral p-i-n photodetectors in Ga/sub 0.47/In/sub 0.53/As and GaAs for 1.3- and 0.85- mu m wavelength operation. The p-type contact and diffusion utilizes W(Zn) metallurgy and the n-type contact and diffusion utilizes MoGe/sub 2/ metallurgy. Bandwidths exceeding 7.5 and 18.0 GHz, respectively, have been obtained using these structures with bias voltages of approximately=5 V. The performance, ease of fabrication, and process compatibility make these devices suitable for integration in digital circuits employing field-effect transistors.<<ETX>>

Lateral p-i-n photodetectors with 18 GHz bandwidth at 1.3 mu m wavelength and small bias voltages

Simultaneous n-type and p-type diffusion, compositional mixing, and formation of ohmic contacts have been used in the fabrication of lateral p-i-n photodetectors for short (0.85 mu m) and long (1.3 mu m and 1.5 mu m) wavelengths. Zinc-doped tungsten and MoGe/sub 2/ are used for the p-type and n-type contacts, doping, and compositional mixing using rapid thermal processing at approximately=750 degrees C. With structures utilizing GaAs and Ga/sub 0.47/In/sub 0.53/As active regions, 3 dB bandwidths exceeding 7.5 GHz and 18.0 GHz, respectively, have been achieved at bias voltages of approximately=5 V. The corresponding dark currents are sub-100 pA and sub-10 nA and the devices exhibit a large dynamic range, near-ideal responsivity, and a high sensitivity. The performance, ease of fabrication, and process compatibility make these devices suitable for integration in digital circuits using FET.<<ETX>>