Thomas Ebi

TAPE: thermal-aware agent-based power economy for multi/many-core architectures

A growing challenge in embedded system design is coping with increasing power densities resulting from packing more and more transistors onto a small die area, which in turn transform into thermal hotspots. In the current late silicon era silicon structures have become more susceptible to transient faults and aging effects resulting from these thermal hotspots. In this paper we present an agent-based power distribution approach (TAPE) which aims to balance the power consumption of a multi/many-core architecture in a pro-active manner. By further taking the systems thermal state into consideration when distributing the power throughout the chip, TAPE is able to noticeably reduce the peak temperature. In our simulation we provide a fair comparison with the state-of-the-art approaches HRTM [19] and PDTM [9] using the MiBench benchmark suite [18]. When running multiple applications simultaneously on a multi/many-core architecture, we are able to achieve an 11.23% decrease in peak temperature compared to the approach that uses no thermal management [14]. At the same time we reduce the execution time (i.e. we increase the performance of the applications) by 44.2% and reduce the energy consumption by 44.4% compared to PDTM [9]. We also show that our approach exhibits higher scalability, requiring 11.9 times less communication overhead in an architecture with 96 cores compared to the state-of-the-art approaches.

Run-time adaptive on-chip communication scheme

During run-time varying workloads and/or constraints in embedded systems require run-time adaptivity to provide a high degree of efficiency during any operation mode/scenario. Design time decisions can often only cover certain scenarios and fail in efficiency when hard-to-predict system scenarios occur. We are presenting the first approach of an adaptive on-chip communication scheme. It provides an adaptive routing/path allocation algorithm to meet a required level of QoS (guaranteed bandwidth). In our architecture adaptive runtime links are established by re-assigning buffer blocks on-demand. This adaptive buffer allocation scheme increases the buffer utilization and decreases the overall buffer use on an average of 42% in our case study analysis compared to a fixed buffer assignment strategy. The area overhead introduced by the adaptive scheme can be traded-off against the flexibility in order to select an available path and on-demand buffer allocation. We demonstrate the advantage by using various real world digital media applications and compare our approach to the state-of-the-art static on-chip communication schemes.

Configurable links for runtime adaptive on-chip communication

Reliability concerns associated with upcoming technology nodes coupled with unpredictable system scenarios resulting from increasingly complex systems require considering runtime adaptivity in all possible parts of future on-chip systems. We are presenting a novel configurable link which can change its supported bandwidth on-demand at runtime (2X-Links) for an adaptive on-chip communication architecture. We have evaluated our results using real-time multi-media and the E3S application benchmark suits. Our 2X-Links provide a higher throughput of up to 36%, with an average throughput increase of 21.3%, compared to the Normal-Full-Duplex-Links [12], [14], [17], [20] and keep performance-related guarantees with as low as 50% of the Normal-Full-Duplex-Links capacity. Our simulation shows when some links fail, the NoC with 2X-Links can recover from these faults with an average probability of 82.2% whereas these faults would be fatal for the Normal-Full-Duplex-Links.

Towards interdependencies of aging mechanisms

With technology in deep nano scale, the susceptibility of transistors to various aging mechanisms such as Negative/ Positive Bias Temperature Instability (NBTI/PBTI) and Hot Carrier Induced Degradation (HCID) etc. is increasing. As a matter of fact, different aging mechanisms simultaneously occur in the gate dielectric of a transistor. In addition, scaling in conjunction with high-K materials has made aging mechanisms, that have often been assumed to be negligible (e.g., PBTI in NMOS and HCID in PMOS), become noticeable. Therefore, in this paper we investigate the key challenge of providing designers with an abstracted, yet accurate reliability estimation that combines, from the physical to system level, the effects of multiple simultaneous aging mechanisms and their interdependencies. We show that the overall aging can be modeled as a superposition of the interdependent aging effects. Our presented model deviates by around 6% from recent industrial physical measurements. We conclude from our experiments that an isolated treatment of individual aging mechanisms is insufficient to devise effective mitigation strategies in current and upcoming technology nodes. We also demonstrate that estimating reliability due to an individual dominant aging mechanism together with solely considering a single kind of failures, as currently is a main focus of state-of-the-art (e.g., [28], [22]), can result in 75% underestimation on average.

Economic learning for thermal-aware power budgeting in many-core architectures

One of the key challenges for multi-core processors in the nano-CMOS era is dealing with the increased temperatures. It is imperative that peak temperatures are reduced and that heat is spread as evenly on the chip as possible to avoid mutual heating and high thermal gradients between processor cores. Approaches have emerged which share a global power budget among multiple cores in order to meet these objectives. However, while these approaches act proactively in distributing power across the chip before thermal problems arise, changes in the respective strategies remain reactive to a temperature threshold. Our approach uses reinforcement learning in order to dynamically change what we call power trading strategies before thermal thresholds are hit based on past recorded observations. Through learning, our hierarchical approach is also able to distribute so-called multiple power budgets at once thereby making power trading more effective, reaching a decrease in peak temperatures of around 4% compared to a fully distributed approach - which can be critical at near-threshold temperatures in terms of transient errors - while also decreasing the number of deadline misses by a factor of 7. Our technique has been verified by deploying a thermal camera.

ROAdNoC: runtime observability for an adaptive network on chip architecture

Hard-to-predict system behavior and/or reliability issues resulting from migrating to new technology nodes requires considering runtime adaptivity in future on-chip systems. Runtime observability is a prerequisite for runtime adaptivity as it is providing necessary system information gathered on-the-fly. We are presenting the first comprehensive runtime observability infrastructure for an adaptive network on chip architecture which is flexible (e.g. in choosing the routing path), hardly intrusive, and requires little additional overhead (around 0.7% of the total link bandwidth). The hardware overhead is negligible, too, and is in fact less than the hardware savings due to resource multiplexing capabilities that are achieved through runtime observability/adaptivity. As an example, our on-demand buffer assignment scheme increases the buffer utilization and decreases the overall buffer requirements by an average of 42% (the buffer area amounts to about 60% of the entire router area [19]) in our case study analysis compared to a fixed buffer assignment scheme [7]. Our runtime observability on an average also increases the connection success rate by 62% compared to the case without runtime observability for the applications from the E3S benchmark suite [6]. We show the advantages obtained through runtime observability and compare with state-of-the art communication-centric designs.

Runtime Thermal Management Using Software Agents for Multi- and Many-Core Architectures

System-level runtime approaches provide a new dimension of variation tolerance in multi- and many-core systems. This article looks into a scalable system-level, dynamic thermal management solution using an agent-based, distributed-application-mapping approach.

AdNoC: Runtime Adaptive Network-on-Chip Architecture

Networsk-on-chip (NoCs) have emerged as a promising on-chip interconnect for future multi/many-core architectures as NoCs are able to scale communication links with the growing number of cores. State-of-the-art NoC designs rely mainly on a static network configuration using fixed routing algorithms and buffer placements. These approaches are not effective in dealing with hard-to-predict system behavior, for instance due to user behavior or varying workloads, since in order for static NoCs to cover these scenarios, they would have to be designed for worst case scenarios. In this paper, we address these problems with a runtime adaptive network-on-chip (AdNoC). Focusing on the architecture-level adaptation, we present an adaptive route allocation algorithm which provides a required level of QoS (guaranteed bandwidth) coupled with an adaptive buffer assignment scheme which reassigns buffer blocks on-demand. Furthermore, the adaptivity requires a comprehensive, hardly intrusive, runtime observability infrastructure, i.e., using monitoring components, in order to gather data on the system state. The area overhead introduced by the adaptive scheme can be traded off against the flexibility gained. Moreover, the area overhead is also reduced by resource multiplexing due to the on-demand buffer assignment at each output port (we achieved on an average 42% buffer saving in our experiments). We demonstrate the advantage by using various digital media applications and compare our approach to the state-of-the-art static NoC architectures e.g., Xpipe, QNoC, and Æthereal.

Stress balancing to mitigate NBTI effects in register files

Negative Bias Temperature Instability (NBTI) is considered one of the major reliability concerns of transistors in current and upcoming technology nodes and a main cause of their diminished lifetime. We propose a new means to mitigate the effects of NBTI on SRAM-based register files, which are particularly vulnerable due to their small structure size and are under continuous voltage stress for prolonged intervals. The conducted results from our technology simulator demonstrate the severity of NBTI effects on the SRAM cells - especially when process variation is taken into account. Based on the presented analysis, we show that NBTI stress in different registers needs to be tackled using different strategies corresponding to their access patterns. To this end, we propose to selectively increase the resilience of individual registers against NBTI. Our technique balances the gate voltage stress of the two PMOS transistors of an SRAM cell such that both are under stress for approximately the same amount of time during operation - thereby minimizing the deleterious effects of NBTI. We present mitigation implementations in both hardware and in software along with the incurred overhead. Through a wide range of applications we can show that our technique reduces the NBTI-induced reliability degradation by 35% on average. This is 22% better than current State-of-the-Art.

Thermal management for dependable on-chip systems

Dependability has become a growing concern in the nano-CMOS era due to elevated temperatures and an increased susceptibility to temperature of the small structures. We present an overview of temperature-related effects that threaten dependability and a methodology for reducing the dependability concerns through thermal management utilizing the concept of aging budgeting.