Thomas Edward Kopley

Key hot-carrier degradation model calibration and verification issues for accurate AC circuit-level reliability simulation

This study provides necessary degradation model calibration and evaluation guidelines required to enable more consistent and effective use of hot-carrier reliability simulation tools. Benchmark results provide strong verification that the AC degradation models are generally accurate if properly calibrated; however, SPICE modeling errors, secondary physical mechanisms and statistical parameter variation are found to impact the simulated results as much as differences in the circuit design itself.

Three Dimensional Single-Walled Carbon Nanotubes

We report a simple fabrication method of creating a three-dimensional single-walled carbon nanotube (CNT) architecture in which suspended CNTs are aligned parallel to each other along the conventionally unused third dimension at lithographically defined locations. Combining top-down lithography with the bottom-up block copolymer self-assembly technique and utilizing the excellent film forming capability of polymeric materials, highly uniform catalyst nanoparticles with an average size of 2.0 nm have been deposited on sidewalls for generating CNTs with 1 nm diameter. This three-dimensional platform is useful for fundamental studies as well as technological exploration. The fabrication method described herein is applicable for the synthesis of other very small 1D nanomaterials using the catalytic vapor deposition technique.

Digital test circuit design and optimization for AC hot-carrier reliability characterization and model calibration under realistic high frequency stress conditions

This study presents one of the first comprehensive examinations of key issues in designing hot-carrier reliability test circuits that can provide realistic stress voltage waveforms, allow access to the internal device nodes, and provide insight about circuit performance sensitivity to hot-carrier damage. New insights about previous test circuit designs are presented and additional new test circuit designs demonstrated. The inherent design trade-offs that exist between realistic waveform generation and internal device accessibility are analyzed and clarified. Recommendations for optimal test-circuit design for hot-carrier reliability characterization and model calibration are proposed.