Paul J. Marcoux

Building-in ESD/EOS reliability for sub-halfmicron CMOS processes

MOSFET design in high performance CMOS technologies is driven primarily by performance requirements and reliability issues such as hot carrier degradation. These requirements generally lead to processes that are inherently weak in terms of ESD and EOS. This paper presents a case of building-in ESD/EOS reliability through nMOSFET drain design for a 0.35 /spl mu/m CMOS process that compromises neither the performance nor the hot carrier reliability. Three process options were considered: nLDD or nDDD ESD implants, and a silicide-block option. The nDDD option for the I/O transistors was chosen as it complied with the performance and reliability (ESD and HCI) specifications and its implementation cost was lower than a silicide-block option. The paper presents data demonstrating the advantages of the nDDD solution over the other alternatives. Particularly, pulsed-EOS and HBM-ESD data, the impact of layout parameters on ESD performance, and hot-carrier data are reviewed.

Key hot-carrier degradation model calibration and verification issues for accurate AC circuit-level reliability simulation

This study provides necessary degradation model calibration and evaluation guidelines required to enable more consistent and effective use of hot-carrier reliability simulation tools. Benchmark results provide strong verification that the AC degradation models are generally accurate if properly calibrated; however, SPICE modeling errors, secondary physical mechanisms and statistical parameter variation are found to impact the simulated results as much as differences in the circuit design itself.

Digital test circuit design and optimization for AC hot-carrier reliability characterization and model calibration under realistic high frequency stress conditions

This study presents one of the first comprehensive examinations of key issues in designing hot-carrier reliability test circuits that can provide realistic stress voltage waveforms, allow access to the internal device nodes, and provide insight about circuit performance sensitivity to hot-carrier damage. New insights about previous test circuit designs are presented and additional new test circuit designs demonstrated. The inherent design trade-offs that exist between realistic waveform generation and internal device accessibility are analyzed and clarified. Recommendations for optimal test-circuit design for hot-carrier reliability characterization and model calibration are proposed.

Patterned implanted buried‐oxide transistor structures

Metal‐oxide‐semiconductor field‐effect transistors have been fabricated with a buried‐oxide layer implanted under only the source and drain regions. Tungsten selectively chemically vapor deposited over the polycrystalline‐silicon gate electrode limited the oxygen‐implanted area and provided a self‐aligned structure. The surface of the source and drain regions was raised above that of the channel by the implanted oxide. The buried oxide formed under the source and drain regions joined smoothly with the surrounding field oxide. Some additional oxide was formed beneath the thermally grown field oxide by the implanted oxygen, and significant field oxide appears to have been removed by sputtering during the implantation. A simplified, nonoptimum, transistor‐fabrication process produced depletion‐mode, n‐channel devices which exhibited transistor action.

Optical Methods For End-Point Detection In Plasma Etching

Plasma etching has become an important technology in the fabrication of integrated circuits. The importance of this technology will increase as the minimum geometry features continue to decrease to the submicron region. Process monitoring is a very desirable feature in maintaining the precise control that is required of plasma etching for VLSI circuits. This paper describes two optical methods of process monitoring and end point detection for plasma etching. Examples are presented for emission spectroscopy, and an optical reflection method. A direct comparison of these methods as end point detection monitors is also made.