Thomas Feudel

Multiple Stress Memorization In Advanced SOI CMOS Technologies

Two distinct stress memorization phenomena in advanced SOI CMOS are reported in this work. Both require a capping layer and anneal, but can be categorized as techniques 1) requiring an amorphized source/drain region and low temperature anneal, and 2) requiring a high temperature anneal, independent of the crystalline state of the Si. Both improve NMOS drive current, and the resulting improvements are additive to >27% NMOS IDSAT improvement. The first phenomenon is previously unreported. It has been identified to be localized in the source/drains, and yields more improvement with multiple offset implantation prior to capping and annealing.

Atomistic simulation of ion implantation and its application in Si technology

Atomistic computer simulations based on the binary collision approximation (BCA) are very well suited to predict the dependence of as-implanted dopant profiles on implant parameters like energy, dose and direction of incidence as well as on the arrangement of oxide, poly-Si and other materials on the single-crystalline Si substrate. In particular channeling effects, the enhanced dechanneling due to accumulation of radiation defects during ion bombardment and due to pre-existing ion-beam-induced defects can be simulated in a reasonable manner. The BCA code Crystal-TRIM was successfully integrated into 1D and 2D process simulators for the Si technology. The application of the trajectory splitting algorithm and the lateral duplication method ensures a high computational efficiency.

Comprehensive analytical expression for dose dependent ion-implanted impurity concentration profiles

We propose an analytical expression for dose dependent ion-implanted impurity concentration profiles using a main function and a tail function. The main function describes the profile near the peak region and the tail function describes the channeling tail profile. The tail function can express various tail lengths with various shapes. We first use a Pearson IV function as the main function, and show that it covers B, BF2, P, AsIn, and Sb ion-implanted impurity concentration profiles in the energy range of 10 to 180 keV and in the full dose range. We also demonstrate that some of the ion-implanted impurity concentration profiles can be expressed with a simpler main function: a Gaussian and a joined half Gaussian function.

Pseudoepitaxial transrotational structures in 14 nm-thick NiSi layers on (001) silicon

In a system consisting of two different lattices, structural stability is ensured when an epitaxial relationship occurs between them and allows the system to retain the stress whilst avoiding the formation of a polycrystalline film. The phenomenon occurs if the film thickness does not exceed a critical value. Here we show that in spite of its orthorhombic structure, a 14 nm-thick NiSi layer can three-dimensionally adapt to the cubic Si lattice by forming transrotational domains. Each domain arises by the continuous bending of the NiSi lattice, maintaining a close relationship with the substrate structure. The presence of transrotational domains does not cause a roughening of the layer, but instead it improves the structural and electrical stability of the silicide in comparison with a 24 nm-thick layer formed using the same annealing process. These results have relevant implications for the thickness scaling of NiSi layers which are currently used as metallizations of electronic devices.

Taking SOI substrates and low-k dielectrics into high-volume microprocessor production

SOI and low-k technologies are rapidly approaching production maturity. This paper highlights several challenges found when moving them from development to high-volume manufacturing. In overcoming these challenges in wafer processing and transistor development, we have achieved yield learning and performance enhancement rates equivalent to or better than conventional technologies.

Compact and comprehensive database for ion-implanted As profile

We succeeded in explaining dose dependent As ion implantation profiles with a Monte Carlo simulation, and extracted parameters for our proposed analytical profile model from the systematic Monte Carlo data. We proposed a compact database to cover energy, dose, rotation, and oxide thickness dependence.

Implementation and optimization of asymmetric transistors in advanced SOI CMOS technologies for high performance microprocessors

Sub-40 nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65 nm and 45 nm PD-SOI CMOS technologies. With optimization, the asymmetric NMOS and PMOS saturation drive currents improve up to 12% and 10%, respectively, resulting in performance at 1.0 V and 100 nA/mum IOFF of NIDSAT=1354 muA/mum and PIDSAT=857 muA/mum. Product-level implementation of asymmetric transistors showed a speed benefit of 12%, at matched yield and improved reliability.

Shallow BF2 implants in Xe-bombardment-preamorphized Si: The interaction between Xe and F

Si(100) samples, preamorphized to a depth of ∼30nm using 20 keV Xe ions to a nominal fluence of 2×1014cm−2 were implanted with 1 and 3 keV BF2 ions to fluences of 7×1014cm−2. Following annealing over a range of temperatures (from 600 to 1130 °C) and times the implant redistribution was investigated using medium-energy ion scattering (MEIS), secondary ion mass spectrometry (SIMS), and energy filtered transmission electron microscopy (EFTEM). MEIS studies showed that for all annealing conditions leading to solid phase epitaxial regrowth, approximately half of the Xe had accumulated at depths of 7 nm for the 1 keV and at 13 nm for the 3 keV BF2 implant. These depths correspond to the end of range of the B and F within the amorphous Si. SIMS showed that in the preamorphized samples, approximately 10% of the F migrates into the bulk and is trapped at the same depths in a ∼1:1 ratio to Xe. These observations indicate an interaction between the Xe and F implants and a damage structure that becomes a trapping sit...

Effect of source/drain-extension dopant species on device performance of embedded SiGe strained p-metal oxide semiconductor field effect transistors using millisecond annealing

This article shows the importance of source/drain extension dopant species on the performance of embedded silicon-germanium strained silicon on insulator p-metal oxide semiconductor field effect transistor (MOSFET) devices, in which the activation was done using only high temperature ultrafast annealing technologies. BF2 and boron were investigated as source/drain extension dopant species. In contrast to unstrained silicon p-MOSFETs, boron source/drain extension implantations enhance device performance significantly compared to devices with BF2 source/drain extension implantations. Measurements show a 30% mobility enhancement and lower external resistance for the devices with boron source/drain extension implantations. The reason for this lies in the amorphization nature of BF2 implantations. Remaining defects after implant annealing affect the stress transfer from the embedded silicon-germanium and the overall hole mobility which leads to the observed performance degradation. Furthermore, TCAD simulation...

Advanced Annealing Schemes for High-Performance SOI Logic Technologies

We have extensively studied the impact of advanced annealing schemes for highperformance SOI logic technologies. Starting with the 130 nm technology node, we introduced spike rapid thermal annealing (sRTA). Continuous temperature reduction combined with implant scaling helped to improve transistor performance and short channel behavior. During the development of the 90 nm technology we evaluated flash lamp and laser annealing (FLA). These techniques became an essential part of the 65 nm node. At this node we also faced major challenges in terms of compatibility with new materials like SiGe as well as the need for reduction of process parameter fluctuations. Scaling will be continued with the 45 nm technology node towards a truly diffusionless process.