Thomas Fritzsch

Thin film integration of passives - single components, filters, integrated passive devices

The increasing demands on future electronic products require more efficient system integration technologies. Especially the package density gap at board level with the high integrated circuits (ICs) on the one hand and the discrete passive components on the other has to be closed by new packaging technologies which integrate the passive components into the substrate, an interposer or the IC itself. This paper presents investigations for the common integration of inductors, resistors, capacitors as well as passive filter structures in a thin film build up, based on copper and benzocyclobutene (BCB). Technologies from wafer level packaging were adapted for manufacturing of the integrated components. The examinations were carried out with special focus on integrated coils and passive filter structures. Build up, design, processing as well as results of the electrical characterization of the integrated components are described in detail. Furthermore, an integrated passive device (IPD) for application as a filter element in the Bluetooth band is presented.

Polyimide based temporary wafer bonding technology for high temperature compliant TSV backside processing and thin device handling

Temporary wafer bonding for thin wafer processing is one of the key technologies of 3D system integration. In this context we introduce the polyimide material HD3007 which is suitable for temporary bonding of silicon wafers to carrier wafers by using a thermo compression process. Coating and bonding processes for 200 mm and 150 mm wafers with and without topography as well as two de-bonding concepts which are based on laser assisted and solvent assisted release processes are presented. Based on tests with temporary bonded 200 mm wafers, we found a very high compatibility of the bonded compound wafers with standard WLP process equipment and work flows suitable for backside processing of “via first” TSV wafers. Processes like silicon back grinding to a remaining thickness of 60 μm, dry etching, wet etching, CMP, PVD, spin coating of resists and polymers, lithography, electro plating and polymer curing were evaluated and are described in detail. Even at high temperatures up to 300°C and vacuum levels up to 10-4 mbar, the temporary bond layer was stable and no delamination occurred. 60 μm thin wafers could be processed and de-bonded without any problems using both release methods. De-bonding times of less than a couple minutes can be realized with laser assisted de-bonding and several minutes with a solvent based release. Compared to glues of other temporary handling systems, the proposed material offers the highest temperature budget for thin wafer backside processing as well as fast and easy de-bonding at room temperature.

Fabrication of application specific integrated passive devices using wafer level packaging technologies

Integrated passives have become increasingly popular in the last years. Especially wafer level packaging technologies offer an interesting variety of different possibilities for the implementation of integrated passive components. In this context particularly the fabrication of integrated passive devices (IPDs) represents a promising solution regarding the reduction of size and assembly costs of electronic systems in package (SiP). These IPDs combine different passive components (R, L, C) in one subcomponent to be assembled in one step by standard technologies like SMD or flip chip. In this paper the wafer level thin film fabrication of such IPDs (WL-IPDs) will be discussed. After a brief overview of the different possibilities for the realization of IPDs using wafer level packaging technologies two fabricated WL-IPDs will be presented. Design, technological realization as well as results from the electrical characterization will be discussed.

Development and evaluation of lead free reflow soldering techniques for the flip chip bonding of large GaAs pixel detectors on Si readout chip

Lead free reflow soldering techniques applying AuSn as well as SnAg electroplated bumps were chosen for the evaluation of the flip chip bonding process for a x-ray pixel detector. Both can be used in pick & place processes with a subsequent batch reflow suitable for high volume production. AuSn solder was selected due to its fluxless bondability, the good wettability and the self-alignment process capability and SnAg solder due to its more ductile behaviour and lower yield stress compared to AuSn. GaAs test chips with daisy chain and four point Kelvin probe structures together with appropriate Si test substrates were designed, manufactured and bumped. Test chips with 55 and 170 mum pitch and different chip sizes (maximum 16.3 down to 4 mm square) were used. AuSn bumps were deposited by electroplating Au first and Sn on top. Au bumps were also formed on substrate side. Two under bump metallizations (UBM) were used for the SnAg samples: Cu and Ni. FE simulation was performed for AuSn and SnAg interconnections and for different chip sizes. A local model was designed for the bump interconnection and a global octant model for the whole assembly. Very high values were calculated for the peel stress using AuSn bumps. SnAg bumps on the other hand showed a 3 to 5 times reduced peel stress dependent on the chip size. A flip chip bonding process setup was carried out for both solder types, AuSn as well as SnAg, with an analysis of the samples by electrical measurements, cross sectioning and SEM. Due to the different coefficients of the thermal expansion (CTE) of GaAs and Si no stable bonding process was found for the AuSn modules as predicted by the FE analysis. With increasing chip size failures like pad lift or cracking of the GaAs were observed. The SnAg samples showed good bonding results. This technology was then selected to assemble test modules for thermal cycling between -55 and +125degC comparing the Cu and Ni UBM. The modules were qualified by electrical monitoring as well as cross sectioning. More than 200 cycles were reached by the 55 mum pitch, 16.3 mm square, bonded GaAs chips and about 400 by the smallest, 4 mm square chips, although no underfilling was used. As failure mode a fracture within the solder was detected. Based on experimental and simulation results functional 256 times256 GaAs pixel detectors with a chip size of 14 times14 mm2 were assembled on Si read out chips using SnAg bumps on a Cu UBM. Finally, these x-ray image sensors were wire bonded to a PCB and successfully tested showing a yield (on pixel-level) of about 98%.

A via last TSV process applied to ATLAS pixel detector modules: proof of principle demonstration

Via last Through Silicon Vias (TSVs) can be exploited to build low material modules for the upgrades of the ATLAS pixel detector at the High Luminosity LHC. To prove this concept a via last TSV process is demonstrated on ATLAS pixel readout wafers. Demonstrator modules featuring 90 μm thin readout chips with TSVs are operated using the connection from the back side of the chip. This paper illustrates the via formation process and the results from the characterization of modules with TSVs.

Low cost wafer-level 3-D integration without TSV

Most of the wafer level 3-D technologies are using Through-Silicon Vias (TSV). The main barriers for these approaches are high cost, issues with electrical isolation within the Si via and the need of high investments for new equipment which is not used in WLP up to now.

A VCSEL-based miniature laser-self-mixing interferometer with integrated optical and electronic components

It has been previously published how, using two separate Vertical-Cavity-Surface-Emitting-Lasers (VCSELs), a miniature laser-Doppler interferometer can be made for quasi-three-dimensional displacement measurements. For the use in consumer applications as PC-mice, the manufacturing costs of such sensors need to be minimized. This paper describes the fabrication of a low-cost laser-self-mixing sensor by integrating silicon and GaAs components using flip-chip technology. Wafer-scale lens replication on GaAs wafers is used to achieve integrated optics. In this way a sensor was realized without an external lens and that uses only a single GaAs VCSEL crystal, while maintaining its quasi-three-dimensional sensor capabilities.

Development of edgeless TSV X-ray detectors

We report about the activity and progress on the development of TSV edgeless detectors at DESY. One part of the development is Through Silicon Via (TSV) technology for the Medipix3RX readout chip (ROC). TSV technology is a concept of connecting readout chips to readout electronics. Instead of wire-bonding which introduces a large dead area, TSV enables connection through the ROC itself. By replacing wire-bonding with TSV, the dead space between detector modules will be reduced from around 7 mm to only 1.6 mm. The thickness of the wafer will be 200 μ m, with a via diameter of 60 μ m. Inside of the via, a 5 μ m thick copper layer will be used as a conducting layer. On the back side of the chip a Redistribution Layer (RDL) will be deposited. For the RDL structure, 5 μ m thick copper with 40 μ m wide conductive lines will be used. Bump bonding of the sensor plus ROC assembly to ceramic readout board will be optimized in terms of material and bonding temperature. The second part of the project is the development of the edgeless sensor units using active edge sensor technology. Active edge sensors have been simulated with Synopsys TCAD for different polarities including p-on-n, p-on-p, n-on-p and n-on-n with p-spray or p-stop for different thicknesses from 150 μ m to 500 μ m. Results show that the bending of the electric field close to the active edge is leading to image distortion on the sensor edge. In addition, the current design of active-edge sensors shows very poor radiation hardness. We are currently working on the development of a radiation hard active-edge sensor with optimized imaging quality. The final goal of this development is to make Large Area Medipix Detector (LAMBDA) with TSV edgeless units.

A germanium hybrid pixel detector with 55μm pixel size and 65,000 channels

Hybrid pixel semiconductor detectors provide high performance through a combination of direct detection, a relatively small pixel size, fast readout and sophisticated signal processing circuitry in each pixel. For X-ray detection above 20 keV, high-Z sensor layers rather than silicon are needed to achieve high quantum efficiency, but many high-Z materials such as GaAs and CdTe often suffer from poor material properties or nonuniformities. Germanium is available in large wafers of extremely high quality, making it an appealing option for high-performance hybrid pixel X-ray detectors, but suitable technologies for finely pixelating and bump-bonding germanium have not previously been available. A finely-pixelated germanium photodiode sensor with a 256 by 256 array of 55μm pixels has been produced. The sensor has an n-on-p structure, with 700μm thickness. Using a low-temperature indium bump process, this sensor has been bonded to the Medipix3RX photoncounting readout chip. Tests with the LAMBDA readout system have shown that the detector works successfully, with a high bond yield and higher image uniformity than comparable high-Z systems. During cooling, the system is functional around -80°C (with warmer temperatures resulting in excessive leakage current), with -100°C sufficient for good performance.

3-D thin chip integration technology - from technology development to application

3-D technologies open a wide range of chip integration possibilities for microelectronic systems. Most of these technologies are using Through-Silicon Vias (TSV). One disadvantage of this technology is the high investment for new equipment and processing cost for Si etching and metallization. The thin chip integration technology (TCI) presented in this paper is based upon existing WLP infrastrcuture: The core component of this planar integration technology is the embedding of ultra-thin chips into a multi layer thin film routing on a larger sized substrate chip on wafer level. All process steps are performed with standard back end equipment used for redistribution and other wafer level packaging technologies. Using advanced grinding and etching technologies thinning of CMOS chips is possible down to a thickness of 20 to 40 microns with high yield. These ultra-thin chips can be integrated into BCB-copper multi layer redistribution on wafer level.