Thomas H. Drayer

A MOdular and Reprogrammable Real-time Processing Hardware, MORRPH

The MORRPH architecture is a general purpose reconfigurable processing unit, primarily designed to solve real time 2D image processing problems. Its robust architecture allows it to be used for other applications including 1D signal processing, 2D cellular automata problems, and 3D image processing. The modular, open ended architecture consists of an M/spl times/N rectangular mesh of processing elements (PEs), called the processing array. Each PE contains a single field programmable gate array (FPGA) chip and interconnections for several support chips. The FPGA chips within the PEs provide an array of logic resources, consisting of combinational logic functions, flip flops and internal chip routing resources. The types of support chips which are included in the PEs are not fixed, they are determined by the requirements of the computational task performed by the MORRPH. These memory, arithmetic, or processing support chips are specified and assembled on the MORRPH board for each particular application that is developed. Currently, the MORRPH architecture is implemented as an adapter card for the Industry Standard Architecture (ISA) computer bus. A constructed prototype with a 23 array of PEs is used in a current machine vision system to perform low level image processing functions. A significant performance increase is obtained by using the MORRPH as a preprocessing unit for the host processing computer. The MORRPH architecture is shown to be an inexpensive solution for relatively simple or very complex real time processing tasks.

A machine vision system forautomatically grading hardwood lumber

Abstract Any automatic system for grading hardwood lumber can conceptually be dividedinto two components. One of these is a machine vision system for locating and identifying grading defects. The other is an automatic grading program that accepts as input the output of the machine vision system and, based on these data, determines the grade of a board. The progress that has been made on developing the first component, the machine vision component, will be reported in this paper. The machine vision system being developed is made up of a subsystem for imaging rough lumber surfaces, a computer vision subsystem for analyzing the image data and identifying grading defects, a materials handling subsystem for moving boards through the imaging devices, a computer for executing the algorithms comprising the computer vision sub-system and, finally, another small computer for controlling all the other components. This paper will describe the progress that has been made on developing all of these components. It will also indicate the directions for future research. A major goal of this research activity is to create a vision technology that will be applicable to not only the grading of hardwood lumber but a number of other forest products related applications as well.

Using multiple FPGA architectures for real-time processing of low-level machine vision functions

In this paper, we investigate the use of multiple field programmable gate array (FPGA) architectures for real-time machine vision processing. The use of FPGAs for low level processing represents an excellent tradeoff between software and special purpose hardware implementations. A library of modules that implement common low-level machine vision operations is presented. These modules are designed with gate-level hardware components that are compiled into the functionality of the FPGA chips. A common input/output interface is created for use in each of the modules, allowing the interconnection of several image processing modules in a parallel or pipelined manner. This new synchronous, unidirectional interface establishes a protocol for the transfer of image and result data between modules. This reduces the design complexity and allows several different low-level operations to be applied to the same input image. A method is developed to partition and compile the design into the hardware resources of multiple FPGA chips. Experimental results verify the efficiency of using common multiple FPGA architectures to implement real-time machine vision processing.

Computer Vision Hardware System for Automating Rough Mills of Furniture Plants

The rough mill of a hardwood furniture or fixture plant is the place where dried lumber is cut into the rough parts that will be used in the rest of the manufacturing process. Approximately a third of the cost of operating the rough mill is the cost of the raw material. Hence any increase in the number of rough parts produced from a given volume of raw material can markedly affect profit margins of a company. To automate this initial cutup requires a computer vision system that can locate and identify surface defects on boards. This paper describes continuing research aimed at developing such a vision system. An important part of this research activity is the design effort going into creating a prototype hardware system, a system that will be able to scan variable width, variable length hardwood boards at industrial speeds of two to three linear feet per second. This system is being designed to handle full length boards up to sixteen feet long. The components of the prototype are a materials handling system, an imaging system, a image processing hardware system, and a software system for performing the necessary recognition tasks and for performing all the necessary control functions. The design of each of these components will be described with the emphasis placed on hardware development.

A development system for creating real-time machine vision hardware using field programmable gate arrays

In this paper, we introduce a new development system for creating real-time image processing hardware using custom computing machines with multiple Field Programmable Gate Array (FPGA) chips. Three distinct processes are accomplished within the development system: design entry, verification, and translation. A library of modules that implement common low-level machine vision functions is used to create complex designs based on a dataflow graph representation. The librarys low-level image processing modules contain both gate-level and chip-level hardware components, of which the gate-level components are compiled into the functionality of available FPGA chips. Standard interfaces are established for input/output of the modules, allowing for the creation of sophisticated software support tools. Experimental results verify the utility of this development system for easily creating real-time machine vision hardware using multiple FPGA-based custom computing machines.

A high performance Micro Channel interface for real-time industrial image processing applications

Data collection and transfer devices are critical to the performance of any machine vision system. The interface described in this paper collects image data from a color line scan camera and transfers the data obtained into the system memory of a Micro Channel-based host computer. A maximum data transfer rate of 20 Mbytes/sec can be achieved using the DMA capabilities of the camera interface. Programmability of the interface provides flexibility in selection of features such as collected field-of-view, data format, collection method, and camera control. System design is such that the speed of the interface allows for the collection of images intended for real-time processing by any available Micro Channel resident processor(s).<<ETX>>