Joseph G. Tront

MT6D: A Moving Target IPv6 Defense

The Internet Protocol version 6 (IPv6) brings with it a seemingly endless supply of network addresses. It does not, however, solve many of the vulnerabilities that existed in Internet Protocol version 4 (IPv4). In fact, privacy-related crimes in IPv6 are made easier due to the way IPv6 addresses are formed. We developed a Moving Target IPv6 Defense (MT6D) that leverages the immense address space of IPv6. The two goals of MT6D are maintaining user privacy and protecting against targeted network attacks. These goals are achieved by repeatedly rotating the addresses of both the sender and receiver. Address rotation occurs, regardless of the state of ongoing sessions, to prevent an attacker from discovering the identities of the two communicating hosts. Rotating addresses mid-session prevents an attacker from even determining that the same two hosts are communicating. The continuously changing addresses also force an attacker to repeatedly reacquire the target node before he or she can launch a successful network attack. Our proof of concept demonstrates the feasibility of MT6D and its ability to seamlessly bind new IPv6 addresses. We also demonstrate MT6Ds ability to rotate addresses mid-session without dropping or renegotiating sessions. Since MT6D operates at the network layer of the protocol stack, it provides a powerful moving target solution that is both platform and application independent.

On using signature registers as pseudorandom pattern generators in built-in self-testing

Signature registers are commonly used to collect test responses in built-in self-testing (BIST). If the contents of signature registers can be used as test patterns, the overall testing time can be reduced due to improved testing parallelism. Moreover, the number of extra registers for implementing BIST could be reduced. Here, the characteristics of the patterns generated by signature registers are studied through analyses as well as experiments. It is shown that the patterns generated by signature registers are rarely repeated when the number of test patterns is relatively small compared to the number of possible patterns. It is also shown that the patterns generated are almost uniformly distributed. Therefore, signature registers can be used effectively as pseudorandom pattern generators. The practicality of using signature registers as pseudorandom pattern generators is investigated by fault simulation experiments using an example circuit. >

Mobile Device Profiling and Intrusion Detection Using Smart Batteries

This paper introduces capabilities developed for a battery-sensing intrusion protection system (B-SIPS) for mobile computers, which alerts when abnormal current changes are detected. The intrusion detection systems (IDSs) IEEE 802.15.1 (Bluetooth) and 802.11 (Wi-Fi) capabilities are enhanced with iterative safe process checking, wireless connection determination, and an automated intrusion protection disconnect ability. The correlation intrusion detection engine (CIDE) provides power profiling for mobile devices and a correlated view of B-SIPS and snort alerts. An examination of smart battery drain times was conducted to ascertain the optimal transmission rate for the B-SIPS client. A 10 second reporting rate was used to assess 9 device types, which were then compared with their corresponding baseline battery lifetime. Lastly, an extensive usability study was conducted to improve the B-SIPS client and CIDE features. The 31 expert participants provided feedback and data useful for validating the systems viability as a complementary IDS for mobile devices.

Computer-Aided Analysis of RFI Effects in Operational Amplifiers

The modified Ebers-Moll model is used to predict RFI effects in the 741 operational amplifier (op amp)-a bipolar linear integrated circuit (IC). RFI susceptibility predictions for RF incident upon the op-amp input terminals are made using a complete model, a macromodel, and a voltage-offset model. Both the batch-mode computer program SPICE 2 and the commercial interactive computer program ISPICE are used. The three sets of calculated results are essentially identical and agree within 4 dB with experimental results measured at 220 MHz. A threshold cannot be given for the RF power level at which a 741 op amp is susceptible to RFI. The level depends upon the op-amp circuit application. For op-amp circuits designed to amplify input signals in the 0.1-to 1.0-V range, RF power levels as large as -15 to + 5 dBm may be required to cause RHI susceptibility problems. For op-amp circuits designed to amplify input signals in the 1-to 10-mV range, RF power levels as low as -55 to -35 dBm may cause RHI susceptibility problems.

A MOdular and Reprogrammable Real-time Processing Hardware, MORRPH

The MORRPH architecture is a general purpose reconfigurable processing unit, primarily designed to solve real time 2D image processing problems. Its robust architecture allows it to be used for other applications including 1D signal processing, 2D cellular automata problems, and 3D image processing. The modular, open ended architecture consists of an M/spl times/N rectangular mesh of processing elements (PEs), called the processing array. Each PE contains a single field programmable gate array (FPGA) chip and interconnections for several support chips. The FPGA chips within the PEs provide an array of logic resources, consisting of combinational logic functions, flip flops and internal chip routing resources. The types of support chips which are included in the PEs are not fixed, they are determined by the requirements of the computational task performed by the MORRPH. These memory, arithmetic, or processing support chips are specified and assembled on the MORRPH board for each particular application that is developed. Currently, the MORRPH architecture is implemented as an adapter card for the Industry Standard Architecture (ISA) computer bus. A constructed prototype with a 23 array of PEs is used in a current machine vision system to perform low level image processing functions. A significant performance increase is obtained by using the MORRPH as a preprocessing unit for the host processing computer. The MORRPH architecture is shown to be an inexpensive solution for relatively simple or very complex real time processing tasks.

An HDL Simulation of the Effects of Single Event Upsets on Microprocessor Program Flow

Simulation experiments for determining the effects of single event upsets on microprocessor program flow are described. A 16 bit microprocessor is modeled using a hardware description language. Using pseudorandom selection of event time and effected flip-flop, SEUs are injected into the microprocessor model. Upset detectors are modeled along with the microprocessor for determination of fault coverage of several candidate fault detection techniques.

Predicting URF Upset of MOSFET Digital IC's

Typical input and output stages for a digital integrated circuit (IC) have been simulated using the electronic circuit analysis program SPICE2. An unwanted radio-frequency (URF) signal is injected into the circuit at the point where the output stage is connected to an input stage. The effects of varying the magnitude, the frequency, and the relative phase angle of the URF source are studied. An example of a system-level analysis based on the electronics-level simulations is also given.

Battery Exhaustion Attack Detection with Small Handheld Mobile Computers

This paper describes a unique battery-sensing intrusion protection system (B-SIPS) for mobile computers, which alerts on power changes detected on small wireless devices, using an innovative Dynamic Threshold Calculation algorithm. B-SIPS enabled hosts are employed as sensors in a wireless network and form the basis of the intrusion detection system (IDS). B-SIPS implementation correlates device power consumption with IEEE 802.11 Wi-Fi and 802.15.1 Bluetooth communication activity. This battery exhaustion, Wi-Fi, and Bluetooth attack detection capability is scalable and complementary with existing commercial and open system network IDSs. Irregular and attack activity is detected and reported to an intrusion detection engine for correlation with existing trace signatures in a database and for forensic investigation by a security manager.

Effects of Wi-Fi and Bluetooth Battery Exhaustion Attacks on Mobile Devices

This paper provides insight into the ramifications of battery exhaustion Denial of Service (DoS) attacks on battery-powered mobile devices. Several IEEE 802.11 Wi-Fi, IEEE 802.15.1 Bluetooth, and blended attacks are studied to understand their effects on device battery lifetimes. In the worst case, DoS attacks against mobile devices were found to accelerate battery depletion as much as 18.5%. Also presented in this work is a hybrid Intrusion Detection System (IDS) designed to thwart this form of malicious activity; Multi-Vector Portable Intrusion Detection System (MVP-IDS). MVP-IDS combines host-based device instantaneous current (IC) monitoring with attack traffic signaturing modules.

Automatic insertion of BIST hardware using VHDL

A system is presented which automatically inserts BIST (built-in self-testing) hardware to a circuit described in VHDL (VHSIC Hardware Description Language). An appropriate VHDL modeling style for automatic insertion of BIST hardware is investigated. The use of BILBO (built-in logic block observer) is primarily pursued in the system. Algorithmic and rule-based approaches are used in the insertion of BILBO. Test scheduling and control signal distribution are also performed by the system.<<ETX>>