Thomas Lenart

High-resolution digital transmission microscopy—a Fourier holography approach

A spherical reference field is used to construct a digital holography system with a demonstrated resolution down to 228 line pairs per mm. The reference field origin from a GRIN lens placed 1mm from the illuminated object. This allows the use of a standard sensor to record the hologram with the required numerical aperture. The image is determined by evaluation of the Rayleigh-Sommerfeld diffraction integral that relates the object field in the image plane to the object field in the sensor plane. Experimental results are given for two charge couple device sensors and one complementary metaloxide- semiconductor active pixel sensor.

Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores

This paper presents architectures for supporting dynamic data scaling in pipeline fast Fourier transforms (FFTs), suitable when implementing large size FFTs in applications such as digital video broadcasting and digital holographic imaging. In a pipeline FFT, data is continuously streaming and must, hence, be scaled without stalling the dataflow. We propose a hybrid floating-point scheme with tailored exponent datapath, and a co-optimized architecture between hybrid floating point and block floating point (BFP) to reduce memory requirements for 2-D signal processing. The presented co-optimization generates a higher signal-to-quantization-noise ratio and requires less memory than for instance convergent BFP. A 2048-point pipeline FFT has been fabricated in a standard-CMOS process from AMI Semiconductor (Lenart and Owall, 2003), and a field-programmable gate array prototype integrating a 2-D FFT core in a larger design shows that the architecture is suitable for image reconstruction in digital holographic imaging

A 2048 complex point FFT processor using a novel data scaling approach

In this paper, a novel data scaling method for pipelined FFT processors is proposed. By using data scaling, the FFT processor can operate on a wide range of input signals without performance loss. Compared to existing block scaling methods, like implementations of Convergent Block Floating Point (CBFP), the memory requirements can be reduced while preserving the SNR. The FFT processor has been synthesized and sent for fabrication in a 0.35 /spl mu/m standard CMOS technology. In netlist simulations, the FFT processor is capable of calculating a 2048 complex point FFT or IFFT in 27 /spl mu/s with a maximum clock frequency of 76 MHz.

A Hardware Acceleration Platform for Digital Holographic Imaging

This paper presents a hardware acceleration platform for image reconstruction in digital holographic imaging. The hardware accelerator executes a computationally demanding reconstruction algorithm which transforms an interference pattern captured on a digital image sensor into visible images. Focus in this work is to maximize computational efficiency, and to minimize the external memory transfer overhead, as well as required internal buffering. The paper presents an efficient processing datapath with a fast transpose unit and an interleaved memory storage scheme. The proposed architecture results in a speedup with a factor 3 compared with the traditional column/row approach for calculating the two-dimensional FFT. Memory sharing between the computational units reduces the on-chip memory requirements with over 50%. The custom hardware accelerator, extended with a microprocessor and a memory controller, has been implemented on a custom designed FPGA platform and integrated in a holographic microscope to reconstruct images. The proposed architecture targeting a 0.13 µm CMOS standard cell library achieves real-time image reconstruction with 20 frames per second.

A complete MP3 decoder on a chip

The paper presents the results from a course project which focused on all levels in ASIC design flow by implementing a complete MP3 decoder. Two student teams developed a decoder targeting ASIC and FPGA, respectively. The ASIC decoder, fabricated in a 0.35 /spl mu/m process from AMI Semiconductor, consumes 40 mW with a supply voltage of 2 V running at 12 MHz. The FPGA decoder has been implemented and verified on a Virtex-II platform.

Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP Applications

This paper presents the design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible mapping of arbitrary applications at system compile-time, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality and flexibility of the proposed architecture is demonstrated through mapping of a radix-22 FFT processor reconfigurable between 32 and 1024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to a traditional DSP and ARM solution.

Teaching digital HW-design by implementing a complete MP3 decoder

This paper describes a project course that focuses on all the different stages in an ASIC design flow. The project starts at algorithm level, followed by architecture selection, netlist generation, down to physical layout, fabrication, and finally verification. The scope of the project, implementing a complete MP3 decoder in VHDL and sending it for fabrication, motivates the students to work hard towards a common goal.

Accelerating Vector Operations by Utilizing Reconfigurable Coprocessor Architectures

To enhance performance of digital signal processing tasks while keeping the flexibility of programmable solutions is a clear motivation for coprocessors implemented as reconfigurable hardware blocks. This paper investigates the applicability of such coprocessors targeting digital signal processing multi-media applications, initially in the field of speech and audio. A tightly coupled coprocessor architecture with reconfigurable datapath and a local memory system is presented. The coprocessor interacts with the main processor through asynchronous FIFOs. Three computational models that provide support for functionality of different granularities to be accelerated are investigated. A speedup in the range of 2 to 46 compared to processor execution is achieved for vector operations and larger kernels such as autocorrelation, block filtering and fast Fourier transform.

Accelerating signal processing algorithms in digital holography using an FPGA platform

This paper describes the implementation of a custom DSP system to accelerate image processing algorithms used in the field of digital holography. The system, implemented on an FPGA platform, is intended for real-time reconstruction of images captured on a large image sensor. Due to the large amount of processing information, it is not possible to perform a HDL simulation of a complete image reconstruction in reasonable time. Instead, a reconfigurable solution is being used for full scale image reconstruction, exhaustive testing of the functionality and for connecting the accelerator to external components, i.e. the image sensor, monitor output device and high-speed memory banks.

A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing

This paper presents a hybrid interconnect network consisting of a local network with dedicated wires and a global hierarchical network. A distributed memory approach enables the possibility to use generic memory banks as routing buffers, simplifies the implementation and reduces the area requirements of routers. A SystemC simulation environment (SCENIC) has been developed to simulate and instrument models, and to setup different topologies and scenarios. Modules are designed as transaction level models to improve design time and simulation speed.