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IEEE Transactions on Components, Hybrids, and Manufacturing Technology | 1991

Enhancement of flip-chip fatigue life by encapsulation

Darbha Suryanarayana; Richard Hsiao; Thomas P. Gall; Jack Marlyn Mccreary

Encapsulation of controlled collapse chip connection (C4) joints, using a filled epoxy resin with a matched coefficient of thermal expansion (CTE), has provided a substantial increase in the life of C4 joints in accelerated thermal cycle (ATC) fatigue testing on both low CTE organic and ceramic chip carriers. The C4 joints are encapsulated by dispensing a bead of the resin along an edge of the chip. The encapsulant flows underneath the chip by capillary action and completely fills the gap between the chip and the substrate. Optimization of the filler size distribution and resin rheology to obtain consistent flow under the chip without any bubbles is discussed. The filler size distribution and flow under the chip are shown in cross sections of several different materials, including low alpha emitting encapsulants for memory applications. Encapsulant formulations are tested by videotaping the flow of encapsulant under transparent quartz chips. The formation of bubbles as the encapsulant flows around the C4 joints and irregularities in the surface of the substrate can clearly be seen. Proper C4 encapsulation provides virtually complete coverage around all C4 connections. C4 life testing over various temperature ranges shows a five to ten times improvement for both memory and logic footprints when the C4 joints are encapsulated. The vast improvement in C4 joint reliability provided by encapsulation allows the C4 technology to be extended to much larger chips or to higher service temperature ranges without conventional distance from neutral point (DNP) constraints. >


electronic components and technology conference | 1990

Flip-chip solder bump fatigue life enhanced by polymer encapsulation

Darbha Suryanarayana; Richard Hsiao; Thomas P. Gall; Jack Marlyn Mccreary

Encapsulation of controlled collapse chip connection (C4) joints, using a filled epoxy resin having a matched coefficient of thermal expansion (CTE), has provided a substantial increase in the life of C4 joints in accelerated thermal cycle (ATC) fatigue testing on both low-CTE organic and ceramic chip carriers. The C4 joints are encapsulated by dispensing a bead of resin along an edge of the chip. The encapsulation flows underneath the chip by capillary action and completely fills the gap between the chip and the substrate. Optimization of the filler size distribution and resin rheology to get consistent flow under the chip without any bubbles is discussed. The filler size distribution and flow under the chip are shown to cross sections of several different materials including low-alpha-emitting encapsulants for memory applications. Novel encapsulant formulations were tested by videotaping the flow of encapsulant under transparent quartz chips. The formation of bubbles as the encapsulant flows around the C4 joints and irregularities in the surface of the substrate can clearly be seen. Proper C4 encapsulation provides virtually complete coverage around all C4 connections. C4 life testing over various temperature ranges show a 5 to 10 times improvement for both memory and logic footprints when the C4 joints are encapsulated. The vast improvement in C4-joint reliability provided by encapsulation allows the C4 technology to be extended to much larger chips or to higher service-temperature ranges without conventional DNP (distance from neural point) constraints.<<ETX>>


Archive | 1991

Method of fabricating nendritic materials

Perminder Singh Bindra; J. J. Cuomo; Thomas P. Gall; Anthony P. Ingraham; Sung K. Kang; Jungihl Kim; Paul A. Lauro; David Noel Light; Voya R. Markovich; Ekkehard F. Miersch; Jaynal Abedin Molla; Douglas O. Powell; John J. Ritsko; George J. Saxenmeyer; Jack A. Varcoe; George Frederick Walker


Archive | 1990

Separable electrical connection technology

Perminder Singh Bindra; J. J. Cuomo; Thomas P. Gall; Anthony P. Ingraham; Sung K. Kang; Jungihl Kim; Paul A. Lauro; David Noel Light; Voya R. Markovich; Ekkehard F. Miersch; Jaynal Abedin Molla; Douglas O. Powell; John J. Ritsko; George J. Saxenmeyer; Jack A. Varcoe; George Frederick Walker


Archive | 1994

Low temperature ternary C4 flip chip bonding method

Thomas P. Gall; Anthony P. Ingraham


Archive | 1996

Method for producing multi-layer circuit board and resulting article of manufacture

Charles Robert Davis; Thomas P. Gall


Archive | 1994

Multilayered circuit board

William T. Chen; Thomas P. Gall; James R. Wilcox; Tien Y. Wu


Archive | 1996

Cap providing flat surface for DCA and solder ball attach and for sealing plated through holes, multi-layer electronic sturctures including the cap

James Steven Kamperman; Thomas P. Gall; David B. Stone


Archive | 1996

Method for making printed circuit board with flush surface lands

Thomas P. Gall; David B. Stone; Russell Thomas White; James R. Wilcox


Archive | 1993

Fabrication tool and method for parallel processor structure and package

Thomas P. Gall; James R. Loomis; David B. Stone; Cheryl L. Tytran; James R. Wilcox

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