Douglas O. Powell

Flip-chip on FR-4 integrated circuit packaging

Technology advances have made it possible to extend the IBM C4 (Controlled Collapse Chip Connection) IC attachment method, also known as flip-chip, to printed circuit boards with low-cost dielectrics, such as FR-4. This new technology is referred to as Flip Chip Attach (FCA). In the past, C4 attachment had been limited to ceramic substrates due to the high temperature (360/spl deg/C) required to renew the low tin solder on the chips, and the need for the substrate to have its thermal expansion relatively closely matched to that of the silicon chip. The development of methods to deposit uniform, small (approximately 1/spl times/10/sup -3/ mm/sup 3/) volumes of eutectic tin/lead solder on printed circuit cards has allowed C4 bumped chips to be reflow soldered to the cards using standard SMT joining time/temperature profiles. The high melt (3-5% tin, balance lead) solder bump on the chip is used simply as a solder wettable device lead in this case. The resulting solder joint is not a true controlled collapse joint, but the process still maintains the self-aligning characteristic of C4, due to the surface tension of the molten eutectic solder and the low mass of the chip. The other enabling technology development for FCA is the use of a controlled expansion epoxy encapsulant between the chip and the substrate to minimize the cyclic strain on the solder joints induced by thermal expansion mismatch between the silicon chip and the FR-4 card. Without the use of such an encapsulant, the thermal cycle fatigue life of the FCA joints would be totally unacceptable, and the technology would be useless. In this paper we will explain how the enabling technologies work to make FCA a viable packaging method, and present reliability data for several different chips using FCA packaging.<<ETX>>

Electrochemical reactions in solder mask of flip chip-plastic ball grid array package

A typical flip chip plastic ball grid array (FC-PBGA) module utilizes a laminate substrate, which has a solder mask layer at the surface and a number of build-up layers. During reliability testing of the assembled chip-laminate modules under elevated temperature, humidity and voltage bias conditions, electrochemical reactions can proceed in the solder mask layer producing various oxidized copper (Cu) compounds and metallic Cu. If metallic Cu dendrites grow from one electrode toward its adjacent electrode, such dendrites can cause electrical leakage. The electrochemical reactions summarized in this paper involve ionic current flow between flip chip attach copper pads, impurity Cl- ions catalyzing Cu corrosion, the state of the solder mask and/or an absence of oxygen. Under the condition of 130°C, 85% relative humidity and 3.7V bias, Cu2+ ions move from an anode (power) or its vicinity toward a cathode (ground). Cu2+ ions are then reduced at the cathode to yield metallic Cu. If the reduced Cu forms a dendrite pointing toward the neighboring anode, the electric field will focus at the tip of the dendrite. Subsequently more Cu2+ ions will move toward the tip of the dendrite so that the dendrite keeps growing toward the anode. Lack of O2 under the highly accelerated stress conditions can also promote such dendrite growth since O2, if present, can be reduced at the cathode where the reduction of Cu2+ ions will decrease accordingly as a total number of electrons consumed for all reduction reactions remain constant. Cu dendrites can also grow from unbiased Cu electrodes due to the combined effect of galvanic cells and bipolar circuits.

Laminate/HDI Die Carriers

The use of more complex components with very high I/O counts has pushed the board fabricator to re-examine techniques for creating smaller vias. Over the last several years, many new or redeveloped processes have appeared on the market. These processes include revised methods of creating holes, such as laser drilling, micro-punching, and mass etching; new methods for additively creating dielectric with via holes using photo-sensitive dielectric materials; and new methods for metallizing the vias such as conductive adhesives and solid post vias. All of these methods share some common traits. They all allow the designer to significantly increase routing density through the use of vias in SMT pads, to reduce size and weight of product, and to improve the electrical performance of the system. These types of boards are generically called, “High Density Interconnects” or HDI.