Thomas Pflueger

S/390 parallel enterprise server generation 3: a balanced system and cache structure

Since initiating the information technology industry-wide transition from bipolar to CMOS technology with the first generation of S/390® processors in 1994, IBM reached another major milestone with the introduction of the third generation in September 1996. The balanced system and cache structure and the modularity of the components of Generation 3 support a wide performance range from a uniprocessor to a high-performance multiprocessing system. Because of this modularity, Generation 4 is also based on this structure.

A flat, timing-driven design system for a high-performance CMOS processor chipset

We describe the methodology used for the design of the CMOS processor chipset used in the IBM S/390 Parallel Enterprise Server-Generation 3. The majority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques. The result is a globally optimized solution without artificial floorplan boundaries. We show that the density in terms of transistors per mm/sup 2/ is comparable to the most advanced custom designs and that the impact of interconnect delay on the cycle time is very small. Compared to custom design, this approach offers excellent turn-around-time and considerably reduces overall effort.

Advanced features in IBM POWER8 systems

The IBM POWER8™ processor includes many innovative features that enable efficient and flexible computing, along with enhancements in virtualization, security, and serviceability. These features benefit application performance, and big data and analytics computing, as well as the cloud environment. Notable features include the capabilities to dynamically and efficiently change the number of threads active on a processor, enhancing application performance via integer vector operations, encryption accelerations, and reference history arrays. Also notable is improved virtual machine density (supporting multiple simultaneous partitions per core and providing fine-grain power management), allowing continuous monitoring of system performance as well as significantly enhanced system RAS (reliability, availability, and serviceability) and security. Each of these features is technologically complex and advanced. This paper provides an in-depth description of some of these features and their exploitation through systems software and middleware. These features will continue to bring value to the system-of-record workloads in the enterprise. They also make POWER8 systems well-suited for serving the needs of newer workloads such as big data and analytics, while efficiently supporting deployment in cloud environments.

Scalable and modular pervasive logic/firmware design

With the advances in semiconductor technology, more and more units such as cores, caches, memory controller, and input/output (I/O) can be integrated on a single processor. The latest generation of the IBM System z® processor family exploits these technology capabilities and integrates four cores, along with several cache, memory, and I/O units on a single die. More parallel units not only promise increased throughput but also add significant complexity to all chip-wide functions such as on-chip communication among the units. Many of the System z reliability, availability, and serviceability features are based on chip-wide functions, which are referred to as pervasive functions. Among others, the pervasive functions include chip initialization, test, control of clocks, monitoring of status information, and error reporting during system operation, as well as system reconfiguration while the system is running. As the complexity of many pervasive functions dramatically grows with the increasing number of integrated units, a new modular and scalable architecture for pervasive functions has been developed for the IBM zEnterprise® 196 processor (central processor (CP) chip) and system controller (SC chip) to cope with these challenges. This paper outlines the architecture for the CP and SC chips as they pertain to pervasive design. We discuss the architecture considerations taken when the new pervasive architecture was devised and elaborate on the implementation. Furthermore, we show how the novel pervasive architecture is used for very-large-scale integration testing, how it supports power management features, and how it facilitates a modular firmware design.

Standard-cell-based design methodology for high-performance support chips

We describe the methodology used for the design of a set of CMOS support chips used in the IBM S/390® Parallel Enterprise Server Generations 3 and 4. The logic design is based on functional units, and the majority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques. Custom library elements are used wherever needed for performance reasons. Using this approach, a density has been achieved that is comparable to those of contemporary custom designs, combined with very attractive turnaround times.