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Featured researches published by Thomas R. Hotchkiss.


IEEE Journal of Solid-state Circuits | 1990

A CMOS RISC CPU designed for sustained high performance on large applications

Jonathan P. Lotz; B. Miller; Eric Delano; Joel D. Lamb; Mark Forsyth; Thomas R. Hotchkiss

A 90-MHz CMOS CPU has been designed for sustained performance in workstation and commercial/technical multiuser applications. The CPU is part of a multichip system that achieves a 60-MHz operating frequency with 15-ns asynchronous SRAMs. Key performance features include a 3.5-ns 32-b adder, low skew on-chip clock buffers, and cycling large off-chip caches at the operating frequency. The chip has been fabricated using a 1.0- mu m CMOS process that utilizes three-level metal and 480000 transistors on a 14*14-mm die. >


international solid-state circuits conference | 1990

A 90 MHz CMOS RISC CPU designed for sustained performance

Darius Tanksalvala; Joel D. Lamb; Michael A. Buckley; B. Long; S. Chapin; Jonathan P. Lotz; Eric Delano; Richard John Luebs; K. Erskine; S. McMullen; Mark Forsyth; R. Novak; T. Gaddis; Doug Quarnstrom; Craig A. Gleason; E. Rashid; Daniel Lee Halperin; L. Sigel; H. Hill; Craig Simpson; D. Hollenbeck; J. Spencer; Robert J. Horning; H. Tran; Thomas R. Hotchkiss; Duncan Weir; Donald Kipp; J. Wheeler; Patrick Knebel; J. Yetter

A CMOS CPU which operates at 90 MHz under typical conditions and implements an existing RISC (reduced-instruction-set-computer) 140-instruction set is described. The processor has been designed for sustained performance for workstation and both commercial and technical multiuser applications. Key performance features include a 3-ns, 32-b adder; low-skew on-chip clock buffers; and cycling off-chip caches at the operating frequency, using industry-standard synchronous static random-access memories (SRAMs). The speeds obtained are comparable to those of many emitter-coupled logic (ECL) implementations. The CPU chip includes the following hardware: integer fetch and execute unit, on-chip split I/D TLBs (translation lookaside buffers) with two-way 64 entries each, control for second-level off-chip TLBs, control for off-chip two-way split I/D writeback caches with single-bit error correction for data, full multiprocessing support hardware, inference for performance analysis and tuning, and a tightly coupled coprocessor interface.<<ETX>>


Archive | 1994

Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus

Craig R. Frink; William R. Bryg; Kenneth K. Chan; Thomas R. Hotchkiss; Robert D. Odineal; James B. Williams; Michael L. Ziegler


Archive | 1994

Queue-based predictive flow control mechanism

Michael L. Ziegler; Robert J. Brooks; William R. Bryg; Craig R. Frink; Thomas R. Hotchkiss; Robert D. Odineal; James B. Williams; John L. Wood


Archive | 1994

Fast pipelined distributed arbitration scheme

Michael L. Ziegler; Robert J. Brooks; William R. Bryg; Kenneth K. Chan; Thomas R. Hotchkiss; Robert E. Naas; Robert D. Odineal; Brendan A. Voge; James B. Williams; John L. Wood


Archive | 2000

Queue-based predictive flow control mechanism with indirect determination of queue fullness

Michael L. Ziegler; Robert J. Brooks; William R. Bryg; Craig R. Frink; Thomas R. Hotchkiss; Robert D. Odineal; James B. Williams; John L. Wood


Archive | 1991

Data cache store buffer for high performance computer.

Thomas R. Hotchkiss; Stephen R. Undy; Daniel Lee Halperin


Archive | 1994

Improved ordered cache-coherency scheme

Craig R. Frink; William R. Bryg; Kenneth K. Chan; Thomas R. Hotchkiss; Robert D. Odineal; James B. Williams; Michael L. Ziegler


Archive | 1995

System for operand bypassing to allow a one and one-half cycle cache memory access time for sequential load and branch instructions

Darius Tanksalvala; Eric Delano; Patrick Knebel; Thomas R. Hotchkiss; R. Craig Simpson


Archive | 1990

Pipeline method and apparatus.

Darius Tanksalvala; Patrick Knebel; Craig Simpson; Eric Delano; Thomas R. Hotchkiss

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