Thomas S. Salter

An Antenna Co-Design Dual Band RF Energy Harvester

RF energy is widely available in urban areas and thus presents a promising ambient energy harvesting source. In this paper, a CMOS harvester circuit is modeled and analyzed in detail at low environmental power levels. Based on the circuit analysis, a design procedure is given for a narrowband energy harvester. The antenna and harvester co-design methodology is discussed to improve RF to DC energy conversion efficiency. We demonstrate that it is difficult to harvest RF energy over a wide frequency band if the ambient RF energy sources are weak, owing to the voltage requirements. Since most ambient RF energy lies in a few narrow bands, a dual/multi-band energy harvester architecture should be able to harvest much of the available RF energy. A dual-band CMOS energy harvester is designed and fabricated using an IBM 0.13 μm process. The simulated and measured results demonstrate a dual-band energy harvester that obtains over 9% efficiency for two different bands (around 900 MHz and around 1900 MHz) at an input power as low as -19.3 dBm. The DC output voltage of this harvester is over 1 V, which can be used to recharge the battery to form an inexhaustibly powered communication system.

A radio-frequency energy harvesting scheme for use in low-power ad hoc distributed networks

While RF energy harvesting has proven to be a viable power source for low-power electronics, it is still a challenge to obtain significant amounts of energy fast and efficiently from the ambiance. Available RF power is usually very weak, resulting in a weak voltage applied to a demodulator to drive it into a region of significant nonlinearity. An RF energy harvesting system consisting of a rectenna, a dc-dc voltage converter, and a novel battery cell is proposed. The rectenna is an integration of an antenna and rectifying diodes. In addition, a switched-capacitor dc-dc voltage converter is integrated on a silicon integrated circuit with energy transfer efficiency as high as 40.5%. A new battery system that can be recharged at low voltage (<; 1.2 V) is demonstrated. In this brief, all of these elements are tested as a system to achieve RF battery recharging from a commercially available hand-held communication device. The system exhibited an overall harvesting efficiency of 11.6%.

A planar dual-band antenna design for RF energy harvesting applications

Past work on radio frequency (RF) energy harvester design mostly focused on harvesting RF energy in a single RF band [1, 2,]. While a significant portion of RF energy is concentrated in the communication band around 900 MHz, there is also abundant RF energy present in the band covering 1800 MHz to 2100 MHz. For example. Li [2011] demonstrated the design and implementation of a dual band RF energy harvester chip that has two cascade voltage multipliers in parallel and can operate at 900 and 1900 MHz bands. The chip can generate 1.2 V output DC voltage at 900 MHz for −19 dBm RF input power and 1.05 V output voltage at 2000 MHz for −18 dBm RF input power. The RF energy conversion efficiency is ∼12% at 900MHz and ∼8% at 2000MHz which is comparable with its single band counterparts at both frequencies in the literature. The design greatly increases the energy harvesting efficiency over two bands. It is found that the input impedance of the chip is ∼ 50 ohm at 900 MHz, 26 ohm at 1.9 GHz, and 70+j10 ohm at 2 GHz. To operate the harvester chip in two bands, the antenna is required to be matched to the chip impedance at 900 MHz for one band and at either 1.9 GHz or 2GHz for the other band.

An integrated low power transceiver system

Wireless sensor networks(WSN) demand low power and low cost transceiver design. In this paper, an integrated transceiver system has been designed and fabricated using a 0.13µm CMOS process for ultra low power WSN applications. The system integrates an OOK receiver, a transmitter, RF/DC switches and a voltage regulator which provides comprehensive on-chip biasing circuitry in a 2×2mm2 chip. A common source low noise amplifier (LNA) works at sub-threshold range to achieve maximum power efficiency. A Villard voltage doubler circuit and a voltage transformer have been used to significantly improve the OOK signal demodulation efficiency and the system sensitivity with near zero power consumption. The system obtains a receiver sensitivity of −60 dBm with 4mW@1.4V.

Ultra low power phase detector and phase-locked loop designs and their application as a receiver

In this paper, we present a new low power down-conversion mixer design with single RF and LO input topology which consumes 48µW power. Detailed analysis of the mixer has been provided. Using the presented mixer as a phase-detector, a low power phase-locked loop (PLL) has been designed and fabricated. A PLL based receiver architecture has been developed and analyzed. The circuit has been fabricated through 0.13µm CMOS technology. Dissipating 0.26mW from a 1.2V supply, the fabricated PLL can track signals between 1.62 and 2.49GHz. For receiver applications, the energy per bit of the receiver is only 0.26nJ making it attractive for low power applications including wireless sensor networks.

Antenna-coupled dual band RF energy harvester design

Radio Frequency (RF) energy harvesting aims at collecting and converting ambient RF wave energy into storable electrical energy to power electronics. The reported RF energy density in urban areas can be as high as 0.5μW/cm2 which corresponds to an input power level of 16.6 μW (−17.6 dBm) at 1800MHz [1]. It is thus appealing to convert the RF energy in the environment into electrical energy and use it to directly power mobile devices, remote sensors data loggers, low power digital applications, or charge batteries [2]. In comparison with conventional battery-based power sources, the RF energy as a source is ubiquitous and can be harvested wirelessly. In addition, the harvesting of RF energy makes use of the amount of energy that will be otherwise wasted. Therefore, it makes use of the RF energy more efficient and is an environmentally friendly practice.

Design of radio frequency energy harvesting system for an unmanned airplane

Energy harvesting is a promising technique that can be used to drive various sorts of passively powered devices [1]. Viable energy sources include wind, sunlight, thermal energy, radio waves, mechanical vibration and so on. As an energy source existing ubiquitously in our environment, radio frequency (RF) energy harvesting has the potential to be widely applied. In this work, an RF energy harvesting system is described for the purpose of driving an unmanned airplane. Eventually, the airplane will be capable of remote recharge and become a self-powered system.

20GHz low power CMOS single chip receiver using resonant transformer techniques for enhanced demodulation efficiency

Smart Dust Systems (SDSs) are typically very low cost wireless ad-hoc networks distributed over a relatively small area which sense, transmit and receive signals. They can be used in applications such as health monitoring, environment sensing and temporal wireless services [1]. The distributed network is composed of wireless nodes, each including antennas, transceivers and digital controllers. Minimizing both cost and power are important requirements for SDS applications. SDSs also require that each node has very small dimensions that are on the cubic millimeter scale. It is difficult to fit an antenna into such a small volume. For example, at 2 GHz, a half-wave dipole antenna is 7.5cm [2]. Using low loss dielectric material, the state of the art FICA (F-Inverted Compact Antenna) at 2.2 GHz has a size of 12mm × 12mm × 3mm [2]. This is still larger than the SDS requirement. Since the chip size is commonly a few mm2, it is clear the antenna size dominates the system size. High frequency operation is a promising way to reduce antenna size since it is inversely proportional to the carrier frequency. For example, theoretically a FICA antenna can be scaled to millimeter range at 20 GHz. To achieve the millimeter size requirements, while also minimizing cost, in this work, we take advantage of CMOS scaling to design an inexpensive 0.13µm CMOS-based amplitude shift keying (ASK) radio frequency receiver that operates at 20 GHz. Resonant transformer circuits which increase voltage levels have also been used to improve system sensitivity [1,3].

Application of a parasitic aware model to optimize an RF energy scavenging circuit fabricated in 130 nm CMOS

Design parameters, including transistor width and number of stacked stages, contribute to the efficiency of RF scavenging systems. This leads to a large design space and, as a result, designing optimal RF scavenging circuits for a given performance requirement is a difficult problem. This work presents an analytical model based on the physical design parameters of the power matched Villard voltage doubler. This model is successfully used to determine the optimal design of an RF energy scavenging circuit fabricated in a 130 nm IBM process.

An analytical model to characterize the input stage of a MOSFET based RF energy harvester for improved impedance matching

RF energy harvesting has been widely investigated as a promising method of providing power to passive wireless devices or recharging the battery used in such systems. The AC input signal which is the ambient RF radiation from the available ISM band is received through the coupled antenna and converted into DC output voltage through the energy harvester chip. The energy harvester, which is a novel resonant boost rectifier circuit, typically consists of multiple stages of voltage doubler stacked in series to achieve a desired output voltage level. In order to achieve maximum rectifier conversion efficiency, it is imperative to have impedance matching between the receiving antenna and the harvester circuit. The input of the harvester is frequently modeled as a resistance in parallel with a capacitance [1]. Therefore, a physical model-based derivation of the equivalent input resistance and capacitance of the rectifier is useful to design an appropriate matching network to resonate out the input capacitance and to match the input resistance to the radiation resistance of the antenna. This paper presents an analytical approach to derive the equivalent input impedance of a multistage voltage doubler circuit designed using short-channel diode-connected MOSFETs.