Thomas Signamarcheix

Enabling 3D interconnects with metal direct bonding

This paper presents the implementation of a key technology developed for high density 3-D integration by circuit stacking. Direct copper bonding at room temperature, atmospheric pressure and ambient air of copper pads allowed the elaboration of a 10×10 9m vertical interconnect with a contact resistance of 10 mohms. First tests on tungsten bonding will be also reviewed.

First integration of Cu TSV using die-to-wafer direct bonding and planarization

Copper-filled Through-Si Vias (TSV) with diameters from 2 µm to 5 µm have been integrated in a die-to-wafer stack combining direct bonding and a planarization technique. TSVs were processed on chip backside after oxide bonding and substrate thinning. The results were compared to the ones achieved with a wafer-to-wafer test vehicle. It was demonstrated that die-to-wafer process developed for this integration does not impact TSV electrical and morphological properties. Moreover, no damage was observed on the stack during TSV process performed at 400°C. This demonstration is the first step to validate the industrial compatibility between high density TSV process and die-to-wafer direct bonding and planarization techniques. With a resistance close to 150 mOhm and a capacitance of about 30 fF, 3 µm-diameter TSV provides excellent electrical performance to heterogeneous 3D ICs.

Challenges and Progress in Germanium-on-Insulator Materials and Device Development towards ULSI Integration

SOITEC, Parc Technologique des Fontaines, F38190, Bernin, France The recent progress in the fabrication of GeOI substrates and devices is reviewed. Improvements have been made in threading dislocation density, Ge-buried oxide interface passivation, device performance. The potential of various co-integration schemes (lateral and vertical) has been illustrated as alternatives to the fabrication of n-type germanium channel devices. GeOI is also shown to be a versatile platform for the monolithic integration of Si and III-V devices and tunneling field effect transistors.

An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling

An innovative die to wafer stacking is proposed for 3D devices. Known good dices are bonded on a processed wafer thanks to direct bonding. Oxide layers or patterned oxide/copper layers are used as the bonding medium. After a first thinning, a low stress high deposition rate oxide is deposited to embed the dices. A final thinning is then done to recover a flat and smooth surface before the trough silicon vias

Germanium oxynitride (GeOxNy) as a back interface passivation layer for Germanium-on-insulator substrates

This paper describes the development of a GeOxNy surface passivation of germanium, which is mandatory for microelectronics germanium-on-insulator (GeOI) substrate fabrication. Indeed, germanium surface reactivity in ambient atmosphere requires the development of Ge surface passivation in order to provide an electrically acceptable interface between the active layer and the buried oxide (BOX) of GeOI substrates. In this paper, GeOI substrates with a passivation interlayer between the Ge film and the BOX were fabricated using the Smart Cut™ technology. Plasma treatments produced a germanium oxynitride (GeOxNy) passivation interlayer with a nitrogen concentration up to 40% and thickness of 3nm. Electrical activity in such GeOI active layer was investigated with pseudo-metal-oxide-semiconductor field effect transistor measurements. Electron mobility reaches a value of 670cm2V−1s−1, notably higher than those typically reported on nonpassivated GeOI structures.

Chip to wafer copper direct bonding electrical characterization and thermal cycling

Copper direct bonding technology is considered to be one of the most promising approach for matching the miniaturization needs of future 3D integrated high performance circuits (3D-IC). In this study, we discuss the recent achievements in copper direct bonding technology with oxide/copper mixed surface and present the latest electrical and physical characterizations of chip to wafer bonding structures after annealing at 400°C and thermal cycling tests. In addition, electrical performance of chip to wafer bonding on 300mm wafers is also presented. Finally, thermo-mechanical finite element simulations showing the impact of the annealing conditions on the closure of the interface are shown.

Crystallographic orientation engineering in silicon-on-insulator substrates

A bilayer silicon-on-insulator film was engineered to locally convert the crystallographic orientation from (100) to (110). The initial bilayer film is composed of a first 50 nm thick (110) oriented Si surface layer, above a second 20 nm thick (100) oriented Si underlayer. The bilayer film was elaborated using hydrophobic bonding to ensure an atomic contact between the two layers without any intermediate oxide. A local and deep-amorphization was developed by ion implantation to amorphize the (100) oriented Si underlayer, conserving also a partially crystalline (110) oriented surface layer. After such a deep amorphization, a solid phase epitaxy regrowth was performed at 900 °C. Transmission electron microscopy observations confirm that the partially crystalline surface layer acts as a seed for the epitaxial regrowth of the amorphized areas through the hydrophobic bonding interface. Thus, the orientation is locally converted from (100) to (110) in the underlayer, which could lead to the elaboration of hybri...

Wafer bonded 4-junction GaInP/GaAs//GaInAsP/GaInAs concentrator solar cells

Multiple-junction solar cells made from III-V compound semiconductors are delivering the highest solar-electric conversion efficiencies. Increasing the number of junctions offers the potential to reach higher efficiencies. Direct wafer bonding offers a unique opportunity to combine lattice mismatched materials through a permanent, electrically conductive and optically transparent interface. In addition, the use of Smart Cut ™ technology, associated with its material recycling capabilities allows from a cost perspective the use of expensive bulk material such as InP. Combination of both technologies opens new opportunities to deliver cost effective high efficiency solar cells. In this respect, we have been able to demonstrate a record efficiency of 44,7% with a wafer bonded 4-junction GaInP/GaAs//GaInAsP/GaInAs concentrator solar cell with bandgap energies of 1.88/1.44//1.11/0.70 eV respectively. The bandgaps are chosen to be close to optimal for conversion under concentrated sunlight [1]. This paper prese...

InP-based composite substrates for four junction concentrator solar cells

A photovoltaics conversion efficiency of 46% at 508 suns concentration was recently demonstrated with a four-junction solar cell consisting in a GaAs-based top tandem cell transferred onto an InP-based bottom tandem cell, by means of wafer bonding. We have successfully produced and characterized different InPOS (for InP-On-Substrate) composite substrates, that could advantageously replace fragile and expensive InP bulk wafers for the growth of the bottom tandem cell. The InPOS composite substrates include a thin top InP layer with thickness below 1µm, transferred onto a host substrate using the Smart Cut™ layer transfer technology. We developed InP-On-GaAs, InP-On-Ge and InP-On-Sapphire substrates with surface and crystal qualities similar to the InP bulk ones. A low electrical resistance of 1.4mΩ.cm² was measured along the InP transferred layer and the bonding interface. An epitaxial bottom tandem cell was grown on an InPOS substrate, and the corresponding PL behavior was found identical to that of cells...

III-V multi-junction solar cell using metal wrap through contacts

The Solar cell front side is a key design point for improved cell efficiency as a trade is made between optical losses (shadowing effect) and electrical losses (resistance). One solution consists in frontside contacts report to the cell’s backside using through device conductive vias. By this way metal shadowing could be drastically reduced without increasing resistive losses. Such architecture is called Metal Wrap Through (MWT) and has been developed on silicon solar cells. Its application to III-V Multi-Junctions Solar Cells (MJSC) could be of great interest and has been simulated and studied for several years. We present here first functional MWT III-V dual-junction solar cells. Prototype developments have been based on inverted tandem solar cell (GaInP/GaAs) epitaxial structures grown on GaAs substrates. Front side contacts have been reported on the device’s backside using specifically adapted Trough Semiconductor Via (TSV) technologies. Finally, the III-V active film was transferred on a conductive r...