Thomas Sri Widodo

FPGA implementation of pipelined 2D-DCT and quantization architecture for JPEG image compression

Two dimensional DCT takes important role in JPEG image compression. Architecture and VHDL design of 2-D DCT, combined with quantization and zig-zag arrangement, is described in this paper. The architecture is used in JPEG image compression. DCT calculation used in this paper is made using scaled DCT. The output of DCT module needs to be multiplied with post-scaler value to get the real DCT coefficients. Post-scaling process is done together with quantization process. 2-D DCT is computed by combining two 1-D DCT that connected by a transpose buffer. This design aimed to be implemented in cheap Spartan-3E XC3S500 FPGA. The 2-D DCT architecture uses 3174 gates, 1145 Slices, 21 I/O pins, and 11 multipliers of one Xilinx Spartan-3E XC3S500E FPGA and reaches an operating frequency of 84.81 MHz. One input block with 8×8 elements of 8 bits each is processed in 2470 ns and pipeline latency is 123 clock cycles.

Temperature response analysis based on pulse width irradiation of 2.45 GHz microwave hyperthermia

This paper describes the temperature response analysis due to the heat effect as a result of microwave hyperthermia irradiation in biological medium for a finite duration time. Since we use the on and off irradiation method, realized by pulse width signal with certain duty cycle value, it is important to know whether the on heating duration can generate sufficient desired heat and the off duration decrease significantly. The bioheat transfer equation and its approximation can help us in analyzing the above relation. According to the analysis and real experiment, our proposed pulse width irradiation with 10s pulse period and its duty cycle variation values used in our 2.45 GHz microwave hyperthermia system can provide sufficient temperature increase during on duration and not significant decrease temperature during off duration, to get the required hyperthermia temperature response.