Thorben Casper

High Dimensional Uncertainty Quantification for an Electrothermal Field Problem using Stochastic Collocation on Sparse Grids and Tensor Train Decomposition

Summary The temperature developed in bondwires of integrated circuits (ICs) is a possible source of malfunction and has to be taken into account during the design phase of an IC. Because of manufacturing tolerances, a bondwires geometrical characteristics are uncertain parameters, and as such, their impact has to be examined with the use of uncertainty quantification methods. Considering a stochastic electrothermal problem featuring 12 bondwire-related uncertainties, we want to quantify the impact of the uncertain inputs onto the temperature developed during the duty cycle of an IC. For this reason, we apply the stochastic collocation method on sparse grids, which is considered the current state-of-the-art. We also implement an approach based on the recently introduced low-rank tensor decompositions, in particular the tensor train decomposition, which in theory promises to break the curse of dimensionality. A comparison of both methods is presented, with respect to accuracy and computational effort.

Increasing EM Robustness of Placement and Routing Solutions based on Layout-Driven Discretization

Nowadays, electromigration (EM) is mainly addressed in the verification step. This is no longer possible due to the ever increasing number of EM failures in the future. An EM-aware physical synthesis could reduce the number of critical locations but the layout complexities prevent this from already being used. To solve this problem, we propose a novel method to discretize placement and routing solutions to enable a fast EM analysis. In addition, we suggest adjustments in the placement and routing step to enhance the EM robustness based on early analysis results. In contrast to the standard approach of running a numerical simulation outside the physical design step and after the synthesis, we perform most of the analysis steps within our placement and routing tools to consider the results; thus enabling early and specialized EM-robust solutions. Particularly, our methodology exploits layout structures to enable an efficient discretization inside the geometrical representations of synthesis tools. We demonstrate how to reduce the discretization effort significantly while achieving sufficient accuracy to improve EM robustness.

Determination of bond wire failure probabilities in microelectronic packages

This work deals with the computation of industry-relevant bond wire failure probabilities in microelectronic packages. Under operating conditions, a package is subject to Joule heating that can lead to electrothermally induced failures. Manufacturing tolerances result, e.g., in uncertain bond wire geometries that often induce very small failure probabilities requiring a high number of Monte Carlo (MC) samples to be computed. Therefore, a hybrid MC sampling scheme that combines the use of an expensive computer model with a cheap surrogate is used. The fraction of surrogate evaluations is maximized using an iterative procedure, yielding accurate results at reduced cost. Moreover, the scheme is non-intrusive, i.e., existing code can be reused. The algorithm is used to compute the failure probability for an example package and the computational savings are assessed by performing a surrogate efficiency study.

Automatic generation of equivalent electrothermal SPICE netlists from 3D electrothermal field models

Starting from a 3D electrothermal field problem discretized by the Finite Integration Technique, the equivalence to a circuit description is shown by exploiting the analogy to the Modified Nodal Analysis approach. Using this analogy, an algorithm for the automatic generation of a monolithic SPICE netlist is presented. Joule losses from the electrical circuit are included as heat sources in the thermal circuit. The thermal simulation yields nodal temperatures that influence the electrical conductivity. Apart from the used field discretization, this approach applies no further simplifications. An example 3D chip package is used to validate the algorithm.