Jens Lienig

introduction to electromigration-aware physical design

Electromigration is increasingly relevant to the physical design of electronic circuits. It is caused by excessive current density stress in the interconnect. The ongoing reduction of circuit feature sizes has aggravated the problem over the last couple of years. It is therefore an important reliability issue to consider electromigration-related design parameters during physical design. In this talk, we give an introduction to the electromigration problem and its relationship to current density. We then present various physical design constraints that affect electromigration. Finally, we introduce components of an electromigration-aware physical design flow.

A parallel genetic algorithm for performance-driven VLSI routing

This paper presents a novel approach to solve the VLSI (very large scale integration) channel and switchbox routing problems. The approach is based on a parallel genetic algorithm (PGA) that runs on a distributed network of workstations. The algorithm optimizes both physical constraints (length of nets, number of vias) and crosstalk (delay due to coupled capacitance). The parallel approach is shown to consistently perform better than a sequential genetic algorithm when applied to these routing problems. An extensive investigation of the parameters of the algorithm yields routing results that are qualitatively better or as good as the best published results. In addition, the algorithm is able to significantly reduce the occurrence of crosstalk.

Electromigration-aware physical design of integrated circuits

The electromigration effect within current-density-stressed signal and power lines is an ubiquitous and increasingly important reliability and design problem in sub-micron IC designs. It is therefore necessary to consider electromigration-related design parameters as early as possible in the physical design flow. In this tutorial, we first give an introduction into the electromigration problem and its relationship to current density and temperature. Physical design parameters that affect current density are presented next. We then focus on various distinctive methodologies that allow the electromigration problem to be addressed directly during physical design and verification of both analog and digital circuits. We also present and discuss commercial applications of these electromigration-aware methodologies.

Electromigration and its impact on physical design in future technologies

Electromigration (EM) is one of the key concerns going forward for interconnect reliability in integrated circuit (IC) design. Although analog designers have been aware of the EM problem for some time, digital circuits are also being affected now. This talk addresses basic design issues and their effects on electromigration during interconnect physical design. The intention is to increase current density limits in the interconnect by adopting electromigration-inhibiting measures, such as short-length and reservoir effects. Exploitation of these effects at the layout stage can provide partial relief of EM concerns in IC design flows in future.

Current-driven wire planning for electromigration avoidance in analog circuits

Electromigration due to insufficient wire width can cause the premature failure of a circuit. The ongoing reduction of circuit feature sizes has aggravated the problem over the last couple of years, especially with analog circuits. It is therefore an important reliability issue to consider current densities already in the physical design stage. We present a new methodology capable of routing analog multi-terminal signal nets with current-dependent wire widths. It is based on current-driven wire planning which effectively determines all branch currents prior to detailed routing. We also discuss successful applications of our methodology in commercial analog circuit design.

Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing

Interconnect with an insufficient width may be subject to electromigration and eventually cause the failure of the circuit at any time during its lifetime. This problem has gotten worse over the last couple of years due to the ongoing reduction of circuit feature sizes. For this reason, it is becoming crucial to address the Problems of current densities and electromigration during layout generation. Here we present two new methodologies capable of routing analog multi-terminal signal nets with current-driven wire widths. Our first approach computes a Steiner tree layout satisfying all specified current constraints before performing a DRC- and current-correct point-to-point detailed routing. The second methodology is based on a terminal tree which defines a detailed terminal-to-terminal routing sequence. We also discuss successful applications of both methodologies in commercial analog circuits.

Assembling 2-D Blocks Into 3-D Chips

Despite numerous advantages of 3-D integrated circuits (ICs), their commercial success remains limited. In part, this is due to the wide availability of trustworthy intellectual property (IP) blocks developed for 2-D ICs and proven through repeated use. Block-based design reuse is imperative for heterogeneous 3-D ICs where memory, logic, analog, and microelectromechanical systems dies are manufactured at different technology nodes and circuit modules cannot be partitioned among several dies. In this paper, we show how to integrate 2-D IP blocks into 3-D chips without altering their layout. Experiments indicate that the overhead of proposed integration is small, which can help accelerate industry adoption of 3-D integration.

A genetic algorithm for channel routing in vlsi circuits

A new genetic algorithm for channel routing in the physical design process of VLSI circuits is presented. The algorithm is based on a problem-specific representation scheme and problem-specific genetic operators. The genetic encoding and our genetic operators are described in detail. The performance of the algorithm is tested on different benchmarks, and it is shown that the results obtained using the proposed algorithm are either qualitatively similar to or better than the best published results.

Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits

Electromigration is caused by high current-density stress in the metallization patterns and is a major source of breakdown in electronic devices. It is, therefore, an important reliability issue to verify current densities within all stressed metallization patterns. In this paper, we propose an efficient methodology for hierarchical verification of current densities in arbitrarily shaped custom-circuit layouts as commonly used in analog circuits and analog blocks in mixed-signal ICs. Our approach includes a quasi-three-dimensional model to verify irregularities, such as vias and incorporates thermal simulation data to account for the temperature dependency of the electrical field configuration and the electromigration process. The described methodology, which can be integrated into any IC design flow as a design rule check, has been successfully tested and verified in commercial design flows.

Interconnect and current density stress: an introduction to electromigration-aware design

Electromigration due to excessive current density stress in the interconnect can cause the premature failure of an electronic circuit. The ongoing reduction of circuit feature sizes has aggravated the problem over the last couple of years. It is therefore an important reliability issue to consider electromigration-related design parameters during interconnect design. In this tutorial, we give an introduction to the electromigration problem and its relationship to current density. We then present various physical design constraints that affect electromigration. Finally, we introduce components of an electromigration-aware physical design flow.