Thorsten Drager

Energy aware compilation for DSPs with SIMD instructions

The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. In this paper we present compiler optimizations with the aim of minimizing energy consumption of embedded applications: This comprises loop optimizations for exploitation of SIMD instructions and zero overhead hardware loops in order to increase performance and decrease the energy consumption. In addition, we use a phase coupled code generator based on a genetic algorithm (GCG) which is capable of performing energy aware instruction selection and scheduling. Energy aware compilation is done with respect to an instruction level energy cost model which is integrated into our code generator and simulator. Experimental results for several benchmarks show the effectiveness of our approach.

Low-energy DSP code generation using a genetic algorithm

This paper deals with low-energy code generation for a highly optimized digital signal processor designed for mobile communication applications. We present a genetic algorithm based code generator (GCG), and an instruction-level power model for this processor. Our code generator is capable of reducing the power dissipation of target applications by means of two techniques. First, GCG minimizes the number of memory accesses by using a special list-scheduling algorithm. This technique makes it possible to perform graph based code selection and to take into account the high interdependencies of the sub-tasks of code generation by phase coupling. In addition, GCG optimizes the scheduling of processor instructions with respect to the instruction-level power model based on a gate level simulation. Experimental results for several benchmarks show the effectiveness of our approach.

Implementing a receiver for terrestrial digital video broadcasting in software on an application-specific DSP

Terrestrial digital video broadcasting (DVB-T) is currently being introduced in many European countries and planned to supplement or replace current analogue broadcasting schemes in a large part of the world. It is also considered as an additional downlink medium for third generation UMTS mobile telephones, where a special variant, DVB-H, is under development. Current DVB-T receivers still are built upon dedicated application specific integrated circuits (ASIC). However, designing ASIC is a tedious and expensive task. We show that it is possible to implement a DVB-T receiver in software on an application-specific digital signal processor (AS-DSP). We analyze the computational requirements of a DVB-T receiver and investigate its potential for parallelization. Further, we present our AS-DSP, the M5-DSP, which is based on a novel architecture and design methodology, and report on implementing the core algorithms of a DVB-T receiver on it.

Using group theory to specify application specific interconnection networks for SIMD DSPs

We introduce another view of group theory in the field of interconnection networks. With this approach it is possible to specify application specific network topologies for permutation data transfers. Routing of data transfers is generated and all possible permutation data transfers are guaranteed. We present the approach by means of a kind of SIMD DSP.

Application-specific permutation networks

This paper examines some aspects of the usage of applications specific interconnection networks for highly parallel processors. The networks are based on permutations. Hence, group theoretic methods may be applied to systematically find good networks. Three methods are presented in this paper: partial Schreier Trees, reduced stabiliser chains, and scaling. These methods allow optimum performance for the application specific transfers, and offer compromises between performance of the remaining transfers, and the effort for finding the solution. The combination of all three methods is shown in a case study with a permutation network for a 16-fold processor.