Tian Tong

A 0.18 mum CMOS Low Power Ring VCO with 1 GHZ Tuning Range for 3-5 GHZ FM-UWB Applications

A 0.18 mum CMOS low power ring VCO for 3-5 GHz FM-UWB system applications is presented. In order to achieve a 1 GHz ultra-wide tuning range while retaining a low power consumption the conventional ring configuration is modified. A detailed analysis of the proposed VCO configuration is presented in terms of oscillating frequency, control performance and phase noise performance. During the design phase several tradeoffs were made between power consumption, phase noise and tuning range. Measurement shows that the proposed VCO configuration can provide a tuning range of 1.4 GHZ at 2.7-4.1 GHz while offering a -70 dBc/Hz phase noise level at a 1 MHz frequency offset. The VCO furthermore shows a good tuning linearity. In total the circuit consumes 9.5 mW

A 0.25μm CMOS Low Power RF Multiplier for Ultra-wide Band System Applications

A low power RF multiplier with ultra-wide signal response band is presented for ultra-wide band system applications such as an UWB demodulator (FM-UWB) or RF-correlator (impulse-radio). The principle of operation and the bandwidth theory is presented and discussed. The practical circuit is implemented using a 0.25μm CMOS process from UMC. The test results show an average gain of 22.5dBV-1at 1.2 GHz and 20.8dBV-1at 3 GHz. Across a full bandwidth of more than 700 MHz the design provides high in-band gain flatness. The circuit consumes a total of 1.3 mA from a 2.5V supply. The total circuit area is 200μmx300μm.

A practical FPGA-based LUT-predistortion technology for switch-mode power amplifier linearization

In the context of wireless communications, power amplifiers raise a number of issues. Mastering the linearity vs. efficiency trade-off is not trivial. Switch-mode power amplifiers can provide high power efficiency. However, they exhibit significant nonlinearities, which make them difficult to apply in modern high linear modulation wireless systems. In order to enable their use in such systems, a LUT-based predistortion technique targeting switch-mode PA linearization is introduced. Particularly the predistortion function derivation for handling the whole input interval of the nonlinearity predistortion is described. A 0.18µm CMOS Class F power amplifier is used as the study-case for testing and evaluating the proposed approach. Matlab and DSP-Builder blocks targeting a Stratix II FPGA simulation results show that the proposed LUT-based predistortion technique effectively improves the linearity of the switch-mode PA with an average EVM of less than 2%.

0.18 μm CMOS RF front-end chipset for FM-UWB based P-PAN receivers

This paper describes the design and implementation of a fully differential RF front-end chipset for a low data rate FM-UWB based P-PAN receiver. The chipset includes an ultra-wideband LNA and a wideband RF demodulator. A 0.18 mum standard CMOS RF process is chosen as the technology vehicle. Measurement and demodulation function verification are presented in the paper. The measurement results show that the presented chipset are able to receive and demodulate FM-UWB RF signals successfully. The chipset achieves a 2.2 GHz (2.3 GHz-4.5 GHz) bandwidth, 2.6 GHz-4GHz carrier frequency and an overall average noise figure of 7 dB. The total current consumption by core circuit is around 6.36 mA using a 1.8 V DC power supply.

A 1.9 GHz CMOS class E power amplifier with +29 dBm output power and 58% PAE

This paper investigates the feasibility of designing a high power, high efficiency class E power amplifier fully integrated in CMOS and accordingly presents the design of a 1.9 GHz two-stage class E power amplifier in a standard 0.25 /spl mu/m CMOS technology. Excluding the final output matching network, all passives of interstage and input matching networks are on-chip components. Working with a 2.5 V supply, the amplifier achieves a simulated 4-29 dBm output power with 58% PAE. With a suitable linearization scheme, the power amplifier can be used in a UMTS transmitter.

Link level prototypes

Chapter 4 described the design and selection of the short range communication air interfaces tailored to Personal Networks application. These air interfaces consist of a low data rate (LDR) FM-UWB system and a high data rate (HDR) MC-SS system. The present chapter focuses on the hardware and software design and implementation that was carried out to prove the aforementioned concepts and to assess the performance of these air interfaces, taking into account all the impairments coming from a real hardware implementation, as well as the impact of real usage conditions.

A 1–5 GHz UWB low noise amplifier in 0.18 µm CMOS

A 1–5 GHz ultra-wideband CMOS low-noise amplifier (LNA) is presented. A common-gate topology is adopted for the input stage to achieve wideband input matching, while a cascode stage is used as the second stage to provide power gain at high frequencies. By using two inductors in the LNA, a small chip area is obtained. The LNA has been fabricated in a standard 0.18 µm CMOS technology. The measured maximum power gain is 13.7 dB, and the noise figure is 5.0–6.5 dB in the frequency band of 1–5 GHz. The measured third order (two-tone) input intercept point (IIP3) is −9.8 dBm at 4 GHz. The LNA consumes 9 mW with a 1.8 V supply, and occupies an area of 0.78 mm2.

A method for measuring substrate noise in the UWB frequency band on lightly doped substrates

A measurement method for characterizing the substrate noise over the ultra-wideband (UWB) frequency band in UWB systems implemented using lightly doped CMOS processes is presented. The measurement structure in this method is based on modified ground-signal-ground (GSG) pads. In addition, the effects of the distance-based substrate resistance and the capacitive coupling between the substrate and the ground of the measurement setup are evaluated by on-wafer measurement of a test chip fabricated in a 0.18 mum lightly doped CMOS process. An equivalent circuit model of the presented measurement structure is given and shows accurate fit. From the measurement results the presented method is shown to provide a measurement band from 3 GHz to 10 GHz. To further validate the usability of the method a practical class-E PA is used.

A 0.18 mum CMOS Implementation of a Low Power, Fully Differential RF Front-End for FM-UWB Based P-PAN Receivers

This paper describes the design of a fully differential RF front-end for a low data rate FM-UWB based P-PAN receiver. The RF front-end includes an ultra-wideband LNA and a wideband RF demodulator. The receiver is designed using a standard six metal layer 0.8 mum CMOS process. The differentially configured LNA provides a 30 dB bandpass gain and offers a 2 GHz -10 dB bandwidth. Based on a passive delay component a differential RF delay-line configuration is employed to implement the RF demodulator. A special delay structure is introduced to suppress any phase imbalance in the input signal and thereby improve the gain of the demodulator. Transistor level simulations are presented in the paper and the results show that the proposed RF front-end approach can present 30 dB+50 dBV-1 gain with a 2 GHz -10 dB bandwidth and an overall noise figure of 6 dB. The total current consumption is around 10 mA using a 1.8 V power supply

A 0.18μm CMOS Fully Differential RF Demodulator for FM-UWB Based P-PAN Receivers

In this paper a fully differential implementation of a delay-line RF demodulator for FM-UWB based P-PAN receivers is presented and discussed. The implementation makes use of a dedicated circuit to remove possible phase imbalance in the differential signal pair. Without this correction demodulation performance is seriously affected. Detailed transistor-level simulation results are presented based on a standard 0.18 μm CMOS process. The simulations show that the presented demodulator can provide a 2GHz bandwidth (3-5 GHz) and an overall demodulation gain of 52dBV-1. The circuit consumes 3.2 mA using a 1.8 V power supply