Jan Hvolgaard Mikkelsen

Crosstalk coupling effects of CMOS co-planar spiral inductors

The coupling effects between two adjacent co-planar spiral inductors are characterized in two cases, one where no guard structure is used and one where simple guard-rings are used. In addition, the effect of guard-rings is evaluated at different distances (190 /spl mu/m to 1090 /spl mu/m) between inductors. The model traditionally used to predict this crosstalk is found to be insufficient and an extended model including mutual inductive coupling and direct capacitive coupling is shown to provide accurate fit. Measuring low levels of crosstalk is difficult and in this context the effect of the test fixture itself is evaluated. Return current paths are here found to have significant influence on low frequency results. Also, based on laser cutting of test fixtures, a surrounding ground-ring is found to increase the crosstalk level. The use of simple guard-rings is shown to improve isolation by approximately 10-15 dB for closely spaced adjacent inductors. At larger distances the gain from having a guard-ring reduces and eventually reduces to zero at a distance of 1000 /spl mu/m. For closely spaced devices a doubling of distance is found to provide an additional 20 dB attenuation of crosstalk.

Measurement and modeling of coupling effects of CMOS on-chip coplanar inductors

The coupling effects between two adjacent coplanar spiral inductors are characterized for two cases, one where no guard structure is used and one where simple guard-rings are used. In addition, the effect of guard-rings is evaluated at different distances (190 /spl mu/m to 1090 /spl mu/m) between inductors. Measuring low levels of crosstalk is difficult, and in this context the effect of the test fixture itself is evaluated. Return current paths are found to have significant influence on low frequency results. In addition, based on laser cutting of test fixtures, a surrounding ground-ring is found to increase the crosstalk level. With the effect of ground-ring coupling removed, the use of simple guard-rings is shown to improve isolation by approximately 10-15 dB for closely spaced adjacent inductors. At larger distances, the gain from having a guard-ring reduces and eventually reduces to zero at a distance of 1000 /spl mu/m. For closely spaced devices, a doubling of distance is found to provide an additional 20 dB attenuation of crosstalk. An extended model, including mutual inductive coupling and direct capacitive coupling, is shown to provide an accurate fit.

Investigation of Polar Transmitters for WCDMA Handset Applications

The polar transmitter is an attractive architectural solution for high-efficiency multi-mode handset applications. For the polar transmitter the design of a wide-band phase modulator is a challenging task especially for WCDMA signals. In this work the WCDMA signal is analyzed and based on this a method for solving the frequency jump problem is proposed. This method makes it possible to use a two-point SigmaDelta controlled fractional-N PLL as the phase modulator in polar transmitters for WCDMA. Simulation results in Matlab and ADS show that the proposed pre-processing can reduce the frequency dynamic range and solve the frequency jump problem. This pre-processing degrades the ideal WCDMA signal by a 26dB APCR degradation. There is still 17dB margin to spectral mask requirements

A 3-10 GHz IR-UWB CMOS Pulse Generator With 6-mW Peak Power Dissipation Using A Slow-Charge Fast-Discharge Technique

This letter proposes a UWB pulse generator topology featuring low peak power dissipation for applications with stringent instantaneous power requirements. This is accomplished by employing a new slow-charge fast-discharge approach to extend the time duration of the generators peak current so that the peak value of the current is significantly reduced, while maintaining the waveform of the generated UWB pulse signal. A prototype pulse generator has been implemented using the UMC 0.18 μm CMOS process for validation. The pulse generator offers a 3-10 GHz bandwidth, a maximum pulse repetitive rate of 1 Gpps, a minimum peak power consumption of 6 mW, and a low energy consumption of 5 pJ/pulse. The fabricated pulse generator measures 0.16 mm2.

Modeling and Design Guidelines for

This paper presents a compact model for P+ guard rings in lightly doped CMOS substrates featuring a P-well layer. Simple expressions for the impedances in the model are derived based on a conformal mapping approach. The model can be used to predict the noise suppression performance of P+ guard rings in terms of S-parameters, which is useful for substrate noise mitigation in mixed-signal system-on-chips. Validation of the model has been done by both electromagnetic simulation and experimental results from guard rings implemented using a standard 0.18- μm CMOS process. In addition, design guidelines have been drawn for minimizing the guard ring size while maintaining the noise suppression performance.

{\rm P}^{+}

This brief presents an ultra-wideband pulse generator topology featuring adaptive control of power spectral density for a broad range of applications with different data rate requirements. The adaptivity is accomplished by employing a limited monocycle precharge approach to control the energy used for pulse generation at different desired data rates. By doing so, the need for tuning circuits is eliminated and the radiated power is maintained at the highest level allowed by the Federal Communications Commission. A prototype pulse generator has been implemented using the UMC 180-nm CMOS process for validation. The measured results show that the pulse generator can be used for a wide pulse repetition rate range from 100 Mpps to 1 Gpps. In addition, the pulse generator consumes 0.76 pJ/pulse at 1 Gpps, equivalent to 760 μW and has a compact size of 0.09 mm2.

Guard Rings in Lightly Doped CMOS Substrates

A low power RF multiplier with ultra-wide signal response band is presented for ultra-wide band system applications such as an UWB demodulator (FM-UWB) or RF-correlator (impulse-radio). The principle of operation and the bandwidth theory is presented and discussed. The practical circuit is implemented using a 0.25μm CMOS process from UMC. The test results show an average gain of 22.5dBV-1at 1.2 GHz and 20.8dBV-1at 3 GHz. Across a full bandwidth of more than 700 MHz the design provides high in-band gain flatness. The circuit consumes a total of 1.3 mA from a 2.5V supply. The total circuit area is 200μmx300μm.

A 0.76-pJ/Pulse 0.1–1 Gpps Microwatt IR-UWB CMOS Pulse Generator With Adaptive PSD Control Using a Limited Monocycle Precharge Technique

Abstract New advanced Envelope Tracking (ET) techniques can provide RF (Radio Frequency) transmitters with high-efficiency Power Amplifiers (PAs). On the other hand, system complexity substantially increases, requiring more advanced PA models for the representation and compensation of ET PA distortion effects. In this context, this paper proposes some solutions for behavioral modeling and digital predistortion of ET PAs. The adopted modeling strategy consists in including the modulated supply voltage as an additional independent model variable to define more accurate behavioral models capable of an increased accuracy when applied to model and compensate ET PAs. The new model variable is included in a polynomial model with memory whose nonlinear structure is derived from a binomial power series, whence the name of Memory Binomial Model (MBM). Another modeling approach is subsequently proposed, where the Cann model for static PA AM/AM nonlinearities is extended to model both AM/AM and AM/PM dynamic distortion occurring in ET PAs. The Extended Cann model includes an MBM structure for modeling dynamic AM/PM distortion effects. Both modeling approaches are tested on measured data-sets acquired using an ET measurement set-up including a commercial PA from RFMD and an envelope modulator designed using a commercial IC from Texas Instruments. The measured results showed that the proposed models could obtain a better modeling and predistortion performance when applied to ET PAs, with respect to the Memory Polynomial Model, here considered as a reference to represent the state-of-the-art of PA modeling and digital predistortion.

A 0.25μm CMOS Low Power RF Multiplier for Ultra-wide Band System Applications

Self-heating has already been proven to be one of the key sources to memory effects in RF power amplifiers (PAs). However, mechanisms behind the generation of memory effects, as caused by self-heating have not been well documented. On basis of transistor physical properties this paper proposes a simple electro-thermal model and shows how self-heating can generate different types of memory effects, such as bandwidth dependent intermodulation components and hysteresis loops. In addition, it is shown that self-heating can result in generation of new spectral components even in an otherwise linear PA. A time domain modeling framework is implemented to investigate memory effects generated by self-heating and simulation results are shown to agree with theoretical analysis.

Memory models for behavioral modeling and digital predistortion of envelope tracking power amplifiers

This paper describes the design and implementation of a fully differential RF front-end chipset for a low data rate FM-UWB based P-PAN receiver. The chipset includes an ultra-wideband LNA and a wideband RF demodulator. A 0.18 mum standard CMOS RF process is chosen as the technology vehicle. Measurement and demodulation function verification are presented in the paper. The measurement results show that the presented chipset are able to receive and demodulate FM-UWB RF signals successfully. The chipset achieves a 2.2 GHz (2.3 GHz-4.5 GHz) bandwidth, 2.6 GHz-4GHz carrier frequency and an overall average noise figure of 7 dB. The total current consumption by core circuit is around 6.36 mA using a 1.8 V DC power supply.