Tiansong Cui

Concurrent optimization of consumer's electrical energy bill and producer's power generation cost under a dynamic pricing model

Demand response is a key element of the smart grid technologies. This is a particularly interesting problem with the use of dynamic energy pricing schemes which incentivize electricity consumers to consume electricity more prudently in order to minimize their electric bill. On the other hand optimizing the number and production time of power generation facilities is a key challenge. In this paper, three models are presented for consumers, utility companies, and a third-part arbiter to optimize the cost to the parties individually and in combination. Our models have high quality and exhibit superior performance, by realistic consideration of non-cooperative energy buyers and sellers and getting real-time feedback from their interactions. Simulation results show that the energy consumption distribution becomes very stable during the day utilizing our models, while consumers and utility companies pay lower cost.

Dynamic thermal management for FinFET-based circuits exploiting the temperature effect inversion phenomenon

Due to limits on the availability of the energy source in many mobile user platforms (ranging from handheld devices to portable electronics to deeply embedded devices) and concerns about how much heat can effectively be removed from chips, minimizing the power consumption has become a primary driver for system-on-chip designers. Because of their superb characteristics, FinFETs have emerged as a promising replacement for planar CMOS devices in sub-20nm CMOS technology nodes. However, based on extensive simulations, we have observed that the delay vs. temperature characteristics of FinFET-based circuits are fundamentally different from that of the conventional bulk CMOS circuits, i.e., the delay of a FinFET circuit decreases with increasing temperature even in the super-threshold supply voltage regime. Unfortunately, the leakage power dissipation of the FinFET-based circuits increases exponentially with the temperature. These two trends give rise to a tradeoff between delay and leakage power as a function of the chip temperature, and hence, lead to the definition of an optimum chip temperature operating point (i.e., one that balances concerns about the circuit speed and power efficiency.) This paper presents the results of our investigations into the aforesaid temperature effect inversion (TEI) and proposes a novel dynamic thermal management (DTM) algorithm, which exploits this phenomenon to minimize the energy consumption of FinFET-based circuits without any appreciable performance penalty. Experimental results demonstrate 40% energy saving (with no performance penalty) can be achieved by the proposed TEI-aware DTM approach compared to the best-in-class DTMs that are unaware of this phenomenon.

An electricity trade model for microgrid communities in smart grid

Distributed microgrid network is the major trend of future smart grid, which contains various kinds of renewable power generation centers and a small group of energy users. In the distributed power system, each microgrid acts as a “prosumer” (producer and consumer) and maximizes its own social welfare. In addition, different microgrids can interact among each other through trading over a marketplace. In this paper, two models are introduced for microgrids to deal with the welfare maximization problems. In the first model, a microgrid is considered as a closed economy group and decides the optimal power generation distribution in terms of time. In the second model, each microgrid can trade with its neighborhoods and thus achieve a welfare increase from making use of its comparative advantage on power generation during a certain period of time. For each model, an efficient solution is presented. Experimental result shows the accuracy and efficiency of our presented solutions.

A game-theoretic price determination algorithm for utility companies serving a community in smart grid

Distributed power network is the major trend of future smart grid, which contains multiple non-cooperative utility companies who have incentives to maximize their own profits. The energy price competition forms an n-person game among utility companies where ones price strategy will affect the payoffs of others. More interestingly, the use of dynamic energy pricing schemes incentivizes homeowners to consume electricity more prudently in order to minimize their electric bill. In this paper, two models of price determination are introduced for utility companies under different assumptions. In the first model, a Nash equilibrium solution is presented and the uniqueness of Nash equilibrium point is proved. The second model accounts for more sophisticated factors such as the cost of energy generation and the homeowners reaction to the change of energy usage as a factor of energy price. Although it is no longer possible to prove the uniqueness of Nash equilibrium for the second model, we present a practical solution in which no utility company can increase its expected profit by adjusting the price function. Experimental results show the effectiveness of our two models both in reliability of solution and in runtime.

Negotiation-based task scheduling to minimize user’s electricity bills under dynamic energy prices

Dynamic energy pricing is a promising technique in the Smart Grid that incentivizes energy consumers to consume electricity more prudently in order to minimize their electric bills meanwhile satisfying their energy requirements. This has become a particularly interesting problem with the introduction of residential photovoltaic (PV) power generation facilities. This paper addresses the problem of task scheduling of (a collection of) energy consumers with PV power generation facilities, in order to minimize the electricity bill. A general type of dynamic pricing scenario is assumed where the energy price is both time-of-use and total power consumption-dependent. A negotiation-based iterative approach has been proposed that is inspired by the state-of-the-art Field-Programmable Gate Array (FPGA) routing algorithms. More specifically, the negotiation-based algorithm is used to rip-up and re-schedule all tasks in each iteration, and the concept of congestion is effectively introduced to dynamically adjust the schedule of each task based on the historical scheduling results as well as the (historical) total power consumption in each time slot. Experimental results demonstrate that the proposed algorithm achieves up to 51.8% improvement in electric bill reduction compared with baseline methods.

Optimal control of PEVs for energy cost minimization and frequency regulation in the smart grid accounting for battery state-of-health degradation

Plug-in electric vehicles (PEVs) are considered the key to reducing the fossil fuel consumption and an important part of the smart grid. The plug-in electric vehicle-to-grid (V2G) technology in the smart grid infrastructure enables energy flow from PEV batteries to the power grid so that the grid stability is enhanced and the peak power demand is shaped. PEV owners will also benefit from V2G technology as they will be able to reduce energy cost through proper PEV charging and discharging scheduling. Moreover, power regulation service (RS) reserves have been playing an increasingly important role in modern power markets. It has been shown that by providing RS reserves, the power grid achieves a better match between energy supply and demand in presence of volatile and intermittent renewable energy generation. This paper addresses the problem of PEV charging under dynamic energy pricing, properly taking into account the degradation of battery state-of-health (SoH) during V2G operations as well as RS provisioning. An overall optimization throughout the whole parking period is proposed for the PEV and an adaptive control framework is presented to dynamically update the optimal charging/discharging decision at each time slot to mitigate the effect of RS tracking error. Experimental results show that the proposed optimal PEV charging algorithm minimizes the combination of electricity cost and battery aging cost in the RS provisioning power market.

7nm FinFET standard cell layout characterization and power density prediction in near- and super-threshold voltage regimes

In this paper, we present a power density analysis for 7nm FinFET technology node, including both near-threshold and super-threshold operations. We first build a Liberty-formatted standard cell library by selecting the appropriate number of fins for the pull-up and pull-down networks of each logic cell. The layout of each cell then is characterized based on the lambda-based layout design rules for FinFET devices. Finally, the power density of the 7nm FinFET technology node is analyzed and compared with the state-of-the-art 45nm CMOS technology node for different circuits. Hspice results show that the power density of each 7nm FinFET circuit is at least 10 to 20 times larger than that of the same 45nm CMOS circuit in near- and super-threshold voltage regimes. Also the power densities of FinFET circuits are shown to be much higher than the limit of air cooling, which necessitates careful thermal management for the FinFET technology.

An efficient timing analysis model for 6T FinFET SRAM using current-based method

Accurate timing analysis is a critical step in the design of VLSI circuits. In addition, nanoscale FinFET devices are emerging as the transistor of choice in 32nm CMOS technologies and beyond. This is due to their more effective channel control, higher ON/OFF current ratios, and lower energy consumption. In this paper, an efficient Current Source Model (CSM) is presented to calculate the output waveform as well as the read/write delay of 6T FinFET SRAM cells accounting for noisy waveform at each voltage node. In this model, the non-linear analytical methods and low-dimensional CSM lookup tables (LUTs) are combined to simultaneously achieve high modeling accuracy and time/space efficiency. Experimental data shows that our proposed framework not only provides accurate results in timing analysis, but also can capture the effect of arbitrary voltage noise.

Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells

In this paper, a power density analysis is presented for 7nm FinFET technology node based on both shorted-gate (SG) and independent-gate (IG) standard cells operating in multiple supply voltage regimes. A Liberty-formatted standard cell library is established by selecting the appropriate number of fins for the pull-up and pull-down networks of each logic cell. The layout of both shorted-gate and independent-gate standard cells are then characterized according to lambda-based layout design rules for FinFET devices. Finally, the power density of 7nm FinFET technology node is analyzed and compared with the 45 nm CMOS technology node for different circuits. Experimental result shows that the power density of each 7nm FinFET circuit is 3-20 times larger than that of 45nm CMOS circuit under the spacer-defined technology. Experimental result also shows that the back-gate signal enables a better control of power consumption for independent-gate FinFETs.

An efficient semi-analytical current source model for FinFET devices in near/sub-threshold regime considering multiple input switching and stack effect

Nanoscale FinFET devices are emerging as the transistor of choice in 32nm CMOS technologies and beyond. This is due to their more effective channel control, higher ON/OFF current ratios, and lower energy consumption. This paper presents an efficient current source model (CSM) for FinFET devices operating in the near/sub-threshold regime, considering multiple input switching (MIS) and accounting for the effect of internal node voltages of the logic cell. The main problem of the traditional MIS model is that it requires high-dimensional lookup tables. In this paper, we combine non-linear analytical models and low-dimensional CSM lookup tables to simultaneously achieve high modeling accuracy and time/space efficiency. The proposed framework is verified by experimental results on the 32nm Predictive Technology Model for FinFET devices.