Shahin Nazarian

Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers. The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections. Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues. This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits. The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods

Statistical logic cell delay analysis using a current-based model

A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can accurately compute the output waveform for input waveforms of arbitrary shapes subjected to noise. The cell parasitic capacitances are pre-characterized by lookup tables to improve the accuracy. To capture the effect of process parameter variations on the cell behavior, the output voltage waveform of logic cells is modeled by a stochastic Markovian process in which the voltage value probability distribution at each time instance is computed from that of the previous time instance. Next the probability distribution of a % Vdd crossing time, i.e., the hitting time of the output voltage stochastic process is computed. Experimental results demonstrate the high accuracy of our cell delay model compared to Monte-Carlo-based SPICE simulations

Concurrent optimization of consumer's electrical energy bill and producer's power generation cost under a dynamic pricing model

Demand response is a key element of the smart grid technologies. This is a particularly interesting problem with the use of dynamic energy pricing schemes which incentivize electricity consumers to consume electricity more prudently in order to minimize their electric bill. On the other hand optimizing the number and production time of power generation facilities is a key challenge. In this paper, three models are presented for consumers, utility companies, and a third-part arbiter to optimize the cost to the parties individually and in combination. Our models have high quality and exhibit superior performance, by realistic consideration of non-cooperative energy buyers and sellers and getting real-time feedback from their interactions. Simulation results show that the energy consumption distribution becomes very stable during the day utilizing our models, while consumers and utility companies pay lower cost.

Analyzing crosstalk in the presence of weak bridge defects

An extensive simulation study of various combinations of resistive bridges and crosstalk has been performed and several notable properties that have significant implications for test development have been discovered. Scenarios have been identified where a combination of a bridge at one site and a crosstalk at a separate site in its transitive fanout (or vice versa) can cause slowdown/speed-up whose magnitude significantly exceeds the sum of the slow-down/speed-up, caused by each effect in isolation. It has also been identified that a test vector generated for crosstalk may in fact be invalidated due to the presence of a weak bridge at the crosstalk site. The properties discovered, provide the motivation for a more analytical study that will eventually lead to the proposed framework for test development.

Dynamic thermal management for FinFET-based circuits exploiting the temperature effect inversion phenomenon

Due to limits on the availability of the energy source in many mobile user platforms (ranging from handheld devices to portable electronics to deeply embedded devices) and concerns about how much heat can effectively be removed from chips, minimizing the power consumption has become a primary driver for system-on-chip designers. Because of their superb characteristics, FinFETs have emerged as a promising replacement for planar CMOS devices in sub-20nm CMOS technology nodes. However, based on extensive simulations, we have observed that the delay vs. temperature characteristics of FinFET-based circuits are fundamentally different from that of the conventional bulk CMOS circuits, i.e., the delay of a FinFET circuit decreases with increasing temperature even in the super-threshold supply voltage regime. Unfortunately, the leakage power dissipation of the FinFET-based circuits increases exponentially with the temperature. These two trends give rise to a tradeoff between delay and leakage power as a function of the chip temperature, and hence, lead to the definition of an optimum chip temperature operating point (i.e., one that balances concerns about the circuit speed and power efficiency.) This paper presents the results of our investigations into the aforesaid temperature effect inversion (TEI) and proposes a novel dynamic thermal management (DTM) algorithm, which exploits this phenomenon to minimize the energy consumption of FinFET-based circuits without any appreciable performance penalty. Experimental results demonstrate 40% energy saving (with no performance penalty) can be achieved by the proposed TEI-aware DTM approach compared to the best-in-class DTMs that are unaware of this phenomenon.

A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms

An accurate model is presented to calculate the short circuit energy dissipation of logic cells. The short circuit current is highly dependent on the input and output voltage values. Therefore the actual shape of the voltage signal waveforms at the input and output of the cell should be considered in order to precisely calculate the short circuit energy dissipation. Previous approaches such as the approximation of the crosstalk induced noisy waveforms with saturated ramps can lead to short circuit energy estimation errors as high as an order of magnitude for a minimum sized inverter. To resolve this shortcoming, a current-based logic cell model is utilized, which constructs the output voltage waveform for a given noisy input waveform. The input and output voltage waveforms are then used to calculate the short circuit current, and hence, short circuit energy dissipation. A characterization process is executed for each logic cell in the standard cell library to model the relevant electrical parameters e.g., the parasitic capacitances and nonlinear current sources. Additionally, our model is capable of calculating the short circuit energy dissipation caused by glitches in VLSI circuits, which in some cases can be a key contributor to the total circuit energy dissipation. Experimental results show an average error of about 1% and a maximum error of 3% compared to SPICE for different types of logic cells under noisy input waveforms including glitches while the runtime speedup is up to a factor of 16,000.

XIDEN: crosstalk target identification framework

An efficient crosstalk target identification framework called XIDEN has been developed that is used prior to the computationally expensive processes of crosstalk validation and test generation. XIDEN is mainly composed of a set of extractors and filters that together identify the prime crosstalk targets. These prime targets include all error producing targets, i.e. targets that can potentially create Boolean errors. A methodology has been developed to determine the sequence of extractors and filters to identify a small set of targets with low computational cost. The effects of process variation and extraction accuracy as well as complexity are considered in XIDEN. After performing a training process on sample circuits, XIDEN produces a set of effective extractor filter sequences to be used for production circuits.

An electricity trade model for microgrid communities in smart grid

Distributed microgrid network is the major trend of future smart grid, which contains various kinds of renewable power generation centers and a small group of energy users. In the distributed power system, each microgrid acts as a “prosumer” (producer and consumer) and maximizes its own social welfare. In addition, different microgrids can interact among each other through trading over a marketplace. In this paper, two models are introduced for microgrids to deal with the welfare maximization problems. In the first model, a microgrid is considered as a closed economy group and decides the optimal power generation distribution in terms of time. In the second model, each microgrid can trade with its neighborhoods and thus achieve a welfare increase from making use of its comparative advantage on power generation during a certain period of time. For each model, an efficient solution is presented. Experimental result shows the accuracy and efficiency of our presented solutions.

A game-theoretic price determination algorithm for utility companies serving a community in smart grid

Distributed power network is the major trend of future smart grid, which contains multiple non-cooperative utility companies who have incentives to maximize their own profits. The energy price competition forms an n-person game among utility companies where ones price strategy will affect the payoffs of others. More interestingly, the use of dynamic energy pricing schemes incentivizes homeowners to consume electricity more prudently in order to minimize their electric bill. In this paper, two models of price determination are introduced for utility companies under different assumptions. In the first model, a Nash equilibrium solution is presented and the uniqueness of Nash equilibrium point is proved. The second model accounts for more sophisticated factors such as the cost of energy generation and the homeowners reaction to the change of energy usage as a factor of energy price. Although it is no longer possible to prove the uniqueness of Nash equilibrium for the second model, we present a practical solution in which no utility company can increase its expected profit by adjusting the price function. Experimental results show the effectiveness of our two models both in reliability of solution and in runtime.

Sensitivity-based gate delay propagation in static timing analysis

The paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Conventional STA tools represent an electrical waveform at the intermediate node of a logic circuit by its arrival time and slope. In general, these two parameters are calculated based on the time instances at which the input waveform passes through predetermined voltage levels. However, to account properly for the impact of noise on the shape of a waveform, it is insufficient to model the waveform using only two parameters. The key contribution of the proposed methodology is to base the timing analysis on the sensitivity of the output waveform to the input waveform and accurately, yet efficiently, propagate equivalent electrical waveforms throughout a VLSI circuit. A hybrid technique combines the sensitivity-based approach with an energy-based technique to increase the efficiency of gate delay propagation. Experimental results demonstrate the higher accuracy of our methodology compared to the best of the existing techniques. The sensitivity-based technique is compatible with the current level of gate characterization in conventional ASIC cell libraries, and so it can be easily incorporated into commercial STA tools to enhance their accuracy.