Tiao Zhou

Modeling techniques for board level drop test for a wafer-level package

Reliability performance during drop impact is critical for electronic handheld devices. In this paper, a comprehensive study in efficiency and accuracy of multiple finite element modeling approaches and solution techniques for a wafer-level package (WLP) is presented. JEDEC specified test board is used for the model study. A direct acceleration input method is introduced. Two types of global finite element models for a typical WLP are studied: solder layer and solder bump models. Two different approaches, full implicit dynamics and mode superposition, are applied to solve the JEDEC board dynamic responses. Based on this study, the 8-node solid element with smeared solder layer model, and the full implicit dynamics with either input-G or direct acceleration method are recommend. This combination results in short solution time and produces accurate dynamic solutions for drop test board. It has been found that the fundamental natural frequency of a JEDEC board with WLP typically ranges from 200 to 250 Hz for a large range of array size. There is a large strain gradient close to the component edge for each package on the test board. Due to the rigidity of the silicon chip, the board strain at the center of each component on the opposite side of PCB does not reflect the local bending behaviors of the board. The center of the board between two components might be a stationary point, which does not capture the board bending. With the increase of the chip size, the board strain at edge of each component will increase. The board peak strain at the corner package (U1, U5, U11, and U15) has been found greater than that at the center package (U8), but the bending direction is opposite. The components U6 and U10 have lowest board strains among all components.

Board level temperature cycling study of large array Wafer Level Package

The demand for Wafer Level Packages (WLP) has increased significantly due to its smaller package size and lower cost. However, board level reliability of WLP is still a major concern. This study investigates the board level temperature cycle reliability of three very different wafer level package configurations. Comprehensive studies are carried out through temperature cycle test, failure analysis, and finite element modeling. To assess the wafer level package capability and technology limit, the following parameters are considered: WLP structure, array size, ball locations, ball pitch, and temperature cycle profile.

JEDEC board drop test simulation for wafer level packages (WLPs)

In this paper, a comprehensive study is carried out to investigate the WLP package dynamic behaviors subjected to drop impact according to the JEDEC specification. First, a Direct Acceleration Input (DAI) method, which decouples the board dynamic responses from the test system, thus avoids the difficulties in modeling the complex behaviors of contact between the drop table and drop surfaces, is introduced. The equivalency of the DAI and Input-G methods has been proved mathematically and numerically in this paper. The DAI method removes a rigid-body motion of a test board. Second, the accuracy of global/local modeling techniques is examined in details. Very consistent results were obtained with various distances of cut boundary ranging from 1.5mm to 3.0 mm for the extended PCB board dimension from the package edge. Third, the dynamic responses of each component on JEDEC board are investigated. It is found that for WLP, the component U1, which is the closest to the mounting hole, will fail first due to the local bending effect. This is different from BGA packages. Such results have been validated by recently reported test data. It is noted that the crack initiation of solder ball always starts at the inner side. The corner balls at each component will fail first compared to the balls in other locations on the same components. The maximum peel stress contours for those critical corner balls at each component map the actual solder ball cracks very well. Fourth, the correlation of the board strain to the solder ball stress is studied with different package sizes with or without underfill. It is observed that board strain at the corner locations of component are not always proportional to the damage exerted on solder balls. Therefore caution must be taken when board strain alone is used to evaluate package dynamic performance. Finally, an improved JEDEC board design is proposed to avoid early failure of corner components by moving the screw locations further away from the current specified location. The components at the center column of the modified board will fail first, as observed in many BGA packages. The new board design ensures the package failures come from package intrinsic designs.

3D heterogeneous integration for analog

We illustrate capabilities of 3D integration for analog applications through both wafer-level and packaging technologies. Examples of wafer-level 3D integration include integrated capacitors and optical sensors. Integrated Si capacitors demonstrate the highest reported capacitor density of C=1 μF/mm2 (=1,000 fF/μm2) and the figure of merit (FOM) C*Vbd=11 C/m2 (Vbd is the breakdown voltage). Through-Si vias can be used to combine passive and active die into a single stack. Addition of optical layers to the Bipolar CMOS DMOS (BCD) process allows light detection in the visible and infrared range. 3D package-level integration is illustrated by embedding of multiple active and passive components in one package.

Thermal management for wafer level packaging (WLP)

In this study, the thermal performance of wafer level packaging (WLP) in still air environments is characterized with thermal measurements. Thermal test dice with built-in heaters and temperature sensors are used. Effects of WLP size, WLP design, power dissipation (Pd) area on die, and heat spreaders are investigated. Temperature sensors at different die locations are used to map the die temperature. WLP and board resistance contributions to the overall thermal resistance are also assessed. It is found that WLP package resistance is only a small portion of total junction to ambient thermal resistance. The heat spreading capability of the PCB significantly affects the overall thermal resistance. WLP design details do not make a significant difference since heat spreading in WLP is carried out in Si. Small WLP has higher thermal resistance. Small Pd area results in higher thermal resistance. Furthermore, localized heating causes “hot spots”. Heat spreaders can enhance the thermal performance.