Tiefeng Xu

Low-power adiabatic sequential circuits with complementary pass-transistor logic

This paper presents low-power complementary pass-transistor adiabatic logic (CPAL) using two-phase power-clocks instead of four-phase ones. The two-phase CPAL uses complementary pass-transistor logic for evaluation and transmission gates for energy-recovery. It is more suitable for design of flip-flops and sequential circuits, as it uses fewer transistors than conventional CMOS transmission gate-based implementations and other adiabatic logic circuits such as 2N-2N2P. Adiabatic flip-flops (D, T and JK) based on the two-phase CPAL are introduced. A practical sequential system realized with the proposed adiabatic flip-flops is demonstrated. SPICE simulations show that the two-phase CPAL flip-flops consume less power than 2N-2N2P and CMOS implementation.

Low power dual transmission gate adiabatic logic circuits and design of SRAM

A dual transmission gate adiabatic logic (DTGAL) suitable for driving large capacitance is presented. DTGAL, has no non-adiabatic energy loss on output loads by using feedback control from next-stage buffer outputs. The minimization of energy consumption was investigated by choosing the optimal size of DTGAL circuits. A 64/spl times/64-b adiabatic SRAM is designed. The proposed DTGAL circuits are used to recover the charge of large switching capacitance on bit-lines, word-lines, and address decoders in fully adiabatic manner. The power consumption of the proposed SRAM is significantly reduced as the energy transferred to large capacitance buses is mostly recovered. Energy and functional simulations were performed using the net-list extracted from the layout. HSPICE simulation results indicate that the proposed SRAM attains energy savings of 65% to 90% as compared with the conventional CMOS implementation for clock rates ranging from 25 to 200 MHz.

A CMOS rail-to-rail differential voltage current conveyor and its applications

This paper presents a new CMOS realization of differential voltage current conveyor (DVCC). Rail-to-rail voltage range operation is implemented by using N-type and P-type differential difference input stages. An adaptive voltage offset cancellation technique is presented to ensure exact voltage following performance for rail-to-rail dynamic range. SPICE simulations confirm that the proposed DVCC achieves a rail-to-rail swing under /spl plusmn/2.5 V power supplies and shows the exact voltage and current following performances. The application of the proposed DVCC, which simultaneously provides band-pass and low-pass functions, is also described. Because of its high performance, the proposed DVCC circuit is quite useful as a powerful building block for current-mode circuits.

Power-Gating Techniques for Low-Power Adiabatic Circuits

In adiabatic circuits, the energy dissipation occurs even for constant input signals, as output nodes are always charged and discharged by power-clocks during every cycle. Some adiabatic logic units can be switched off during idle periods to reduce energy loss. This paper presents a new power-gating technique for adiabatic circuits. A power-gating switch with bootstrapped NMOS transistors is used to detach adiabatic logic blocks from power-clocks. The CPAL (complementary pass-transistor adiabatic logic) circuits with the proposed power-gating technique are investigated. SPICE simulations show that energy loss is reduced greatly by shutting down idle adiabatic circuit blocks

A new CMOS differential difference current conveyor and its applications

A new CMOS realization of differential difference current conveyor (DDCC) is presented. The negative feedback action is introduced by using a current mirror to reduce channel length modulation effect of MOS transistors. Furthermore, the circuit is insensitive to the threshold voltage variation caused by the body effect of MOS transistors. Compared with the conventional design, the proposed DDCC circuit has less harmonic distortion and larger linear range. A voltage-mode filter, which simultaneously provides band-pass, high-pass, and low-pass functions, is also described. The proposed DDCC circuit is quite useful as a powerful building block of current-mode circuits because of its high performance, and its application employs fewer passive elements. SPICE simulations confirm the excellent properties of the proposed circuits.

Low power adiabatic multiplier with complementary pass-transistor logic

This paper presents a low-power multiplier based on adiabatic logic. Complementary pass-transistor adiabatic logic (CPAL) circuits are described, and the minimization of energy consumption is investigated by choosing the optimal size of the CPAL circuits. An 8/spl times/8-bit adiabatic multiplier is designed. The organization of the multiplier is identical to the conventional CMOS carry-save multiplier. All the circuits use CPAL to recover the charge of node capacitances. The power consumption of the proposed multiplier, based on CPAL, is significantly reduced, because the non-adiabatic energy loss of output loads has been eliminated using complementary pass-transistor logic for evaluation and transmission gates for energy-recovery. SPICE simulation results indicate energy savings of 70% as compared to the conventional CMOS implementation at 200 MHz.