Yinshui Xia

An Integrated Optimization Approach for Nanohybrid Circuit Cell Mapping

This paper presents an integrated optimization approach for nanohybrid circuit (CMOS/nanowire/molecular hybrid) cell mapping. The method integrates Lagrangian relaxation and memetic search synergistically. Based on encoding manipulation with appropriate population and structural connectivity constraints, 2-D block crossover, mutation, and self-learning operators are developed in a concerted way to obtain an effective mapping solution. In addition, operative buffer insertion is performed to leverage the quality of routing. Numerical results from ISCAS benchmarks and comparison with previous methods demonstrate the effectiveness of the modeling and solution methodology. The method outperforms the previous work in terms of CPU runtime, timing delay, and circuit scale.

CMOL cell assignment by genetic algorithm

We present a genetic algorithm for cell assignment of CMOL, a hybrid CMOS/molecular circuit architecture. We introduce a two dimensional block partially mapped crossover operator as well as mutation operator for our genetic algorithm and conducted experiments using the ISCAS benchmarks. Empirical results indicate our method has faster CPU runtime, has better (more compact) area utilization, and can handle much larger benchmarks than prior methods.

A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping

The article presents the principle of operation of a coupled three-phase reactor (CTRλ) used applied in 18-pulse diode converter. Using sets of coupled three-phase power network reactors, the presented converter makes it possible to considerably reduce, at low cost, undesired higher harmonics in the power network current. Selected results of laboratory tests done on a 20kVA 18-pulse diode converter are included.This paper considers a cell mapping task of CMOL, a hybrid CMOS/molecular circuit architecture. To tackle the combinatorial hurdle arising from the structural connectivity domain constraint, a memetic computing algorithm is developed. The framework takes advantage of simulated annealing based local search strategy and appropriate population based encoding manipulation. Numerical results from ISCAS benchmarks and comparison with pure genetic approach illustrate the effectiveness of the modeling and solution methodology. In terms of CPU runtime, timing delay and circuit scale, the proposed method has better performance than previous methods.

Electrical Modeling and Analysis of a Mixed Carbon Nanotube Based Differential Through Silicon via in 3-D Integration

Based on the extracted equivalent parasitic parameters, the distributed transmission line model of a mixed carbon nanotube bundle (MCB) built signal-ground-signal-type differential through silicon via (TSV) is established and validated against the multiconductor transmission line model (MTL) results and predictive experiment results over a wide frequency range. Using the proposed model, the effect of various dimensional parameters and material properties on the signal loss and characteristic impedances of the differential TSV interconnect is investigated for odd- and even-mode signal propagation, respectively. It is observed that dielectric thickness is the most important factor affecting the transmission characteristics of TSV interconnects for the proposed TSV configuration. Moreover, various electrical performances of the proposed differential TSV, such as insertion loss, eye opening area, characteristic impedances, and 50% time delay are evaluated and compared to that of a signal-ground-type single ended TSV interconnect. The results presented in this paper will be helpful to fully understand the CNT-TSV electrical characterization and provide some signal integrity-aware guidelines for circuit designers in early planning stage.

Study of Crosstalk Effect on the Propagation Characteristics of Coupled MLGNR Interconnects

Multi-layer graphene nanoribbons (MLGNRs) material has been a potential solution to replace conventional Cu for next-generation on-chip interconnects. Based on equivalent single conductor model, this paper extracts the equivalent resistance-inductance-capacitance parameters for MLGNRs with consideration of edge roughness and Fermi level. A distributed circuit model for a pair of coupled MLGNR interconnects is provided, with both capacitive and inductive coupling taken into account, and validated against the Spice results and the predicted experiment results in frequency and time domains. Using the proposed model, the impact of various dimensional and technology parameters on the transfer gain and crosstalk delay is investigated for the global MLGNR interconnects at different phase modes. It is demonstrated that MLGNR interconnects with smooth edge exhibit higher transfer gain and lower crosstalk delay in comparison to its Cu counterpart at same dimension. However, edge roughness in the present fabrication technologies is inevitable that significantly deteriorates the propagation performance and the performance difference due to edge roughness is relatively less in wider MLGNR interconnects. Moreover, it is shown that side contact MLGNR interconnects have better electrical performance than that of top contact MLGNR interconnects at short interconnect length in comparison to that at long interconnects due to the domination of in-layer resistance. The results presented in this paper would be helpful to fully understand the propagation characteristics and provide guidelines for signal integrity analysis of MLGNR interconnects.

Cell Mapping for Nanohybrid Circuit Architecture Using Genetic Algorithm

Nanoelectronics constructed by nanoscale devices seems promising for the advanced development of integrated circuits (ICs). However, the lack of computer aided design (CAD) tools seriously hinders its development and applications. To investigate the cell mapping task in CAD flow, we present a genetic algorithm (GA) based method for Cmos/nanowire/MOLecular hybrid (CMOL), which is a nanohybrid circuit architecture. By designing several crossover operators and analyzing their performance, an efficient crossover operator is proposed. Combining a mutation operator, a GA based algorithm is presented and tested on the International Symposium on Circuits and Systems (ISCAS) benchmarks. The results show that the proposed method not only can obtain better area utilization and smaller delay, but also can handle larger benchmarks with CPU time improvement compared with the published methods.

Study on crosstalk characteristic of carbon nanotube through silicon vias for three dimensional integration

Coupling noise induced by through silicon vias (TSVs) is expected to be a major concern for three dimensional integrated circuits (3-D ICs) system design. Using equivalent electrical parameters for carbon nanotube (CNT) TSV interconnects, a lumped crosstalk noise model is introduced to capture the TSV-to-TSV coupling noise in CNT via based 3-D ICs and validated with multiple conductor transmission line (MTL) simulation results. The effect of geometrical and material parameters involved on the noise transfer function and peak crosstalk noise, such as insulation thickness, TSV-TSV spacing, TSV height, TSV radius, substrate conductivity and metallic CNT density, is investigated with the proposed model. Simulation results show that the TSV coupling can be divided into three frequency behavior regions. Three approaches using driver sizing, grounded vias shielding and air gap-based silicon-on-insulator (SOI) technique are proposed to mitigate TSV crosstalk coupling noise. The proposed approaches are demonstrated in frequency- and time- domain simulations. They provide the reduction in full-band noise transfer function by an average of 11.71dB, 24.85dB and 3.46dB, and the decrease in 1GHz peak noise voltage by 53.24mV, 40.72mV and 15.1mV.

An efficient self-powered synchronous electric charge extraction interface circuit for piezoelectric energy harvesting systems:

Harvesting ambient vibration energy using piezoelectric elements is a popular energy harvesting technique. Energy harvesting efficiency is the research focus. Using synchronous electric charge extraction technology in piezoelectric energy harvesting systems can greatly improve the energy harvesting efficiency. This article presents a self-powered efficient synchronous electric charge extraction circuit for piezoelectric energy harvesting systems, in which four self-powered switch circuits are used to optimize the time sequence of charge extraction so that the rectifier bridge circuit used in traditional synchronous electric charge extraction can be saved. The effect of phase lag on extraction efficiency, system energy, and loss of overall circuit is analyzed. A piezoelectric vibration experimental platform is built for testing the power generation performance of the self-powered efficient synchronous electric charge extraction and those published energy harvesting circuits. The experimental results accord with the theoretical analysis. Moreover, the harvesting energy of the proposed self-powered efficient synchronous electric charge extraction is about three times more than those of the standard energy harvesting circuit under its maximum power point and the self-powered synchronized switch harvesting on inductor in most cases. The energy harvesting efficiency of self-powered efficient synchronous electric charge extraction remains at a high level (>80%) in most cases, and the maximum energy harvesting efficiency is up to 85.1%.

CMOL cell assignment based on dynamic interchange

A new method based on dynamic interchange for cell assignment task of CMOL, a hybrid integrated circuit architecture, is proposed. In this paper, we first transform AND/OR/NOT gates composed of logic circuits into NOT gates and two inputs NOR gates, and then map the NOR/NOT gates to CMOL cells. During mapping process, we first allocate adequate CMOL cell resources and then randomly map the gates to the CMOL cells, which can satisfy the architecture demand and require no overlap between cells. Then we adjust the gates by interchanging and inserting buffers for long distance gate pair. Experiment results on MCNC benchmark show that the proposed approach can result in faster running time than prior approaches1.

Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence

With the ever-increasing power demands of consumer electronics and portable devices, multi-supply voltage (MSV) technique is supposed as one of the direct and effective ways for power optimization in SoC designs. To realize MSV implementation, procedures such as voltage assignment, voltage island partitioning and level shifters (LSs) placement should be considered simultaneously during the floorplanning stage. Although many works addressed the MSV-driven design problem, few of them actually took account of LS placement, which makes the generated results may limit the potential applications. Furthermore, existing design frameworks are often very computationally expensive, and it is not beneficial to shorten the time to market. In this paper, we present an MSV-driven SoC floorplanning framework for fast design convergence. Several techniques are proposed and integrated into an efficient and flexible non-randomized floorplanning algorithm. Firstly, to reserve the desired deadspace for the placement of LSs, the netlist is modified by assigning virtual LSs in the nets. Secondly, a heuristic based voltage assignment method is presented for accuracy and execution time trade-off. Thirdly, different from previous works which do voltage assignment without physical information feedback, an inner loop is built between voltage assignment and LS placement under the constraints of both timing and physical layout. Experimental results on Gigascale Systems Research Center (GSRC) benchmark suites indicate the proposed approach can improve power saving by 12%, CPU time by 48% with 4% area increase. HighlightsA heuristic-based voltage assignment algorithm is proposed for accuracy and CPU time balance.Virtual LSs are assigned in the netlist to reserve the required deadspace for LS placement.Voltage assignment and LS placement are operated iteratively to satisfy timing and physical constraints.The proposed algorithms are integrated into a highly efficient floorplanning algorithm for fast design convergence.