Tilak Agerwala

SP2 system architecture

Scalable parallel systems are increasingly being used today to address existing and emerging application areas that require performance levels significantly beyond what symmetric multiprocessors are capable of providing. These areas include traditional technical computing applications, commercial computing applications such as decision support and transaction processing, and emerging areas such as “grand challenge” applications, digital libraries, and video production and distribution. The IBM SP2™ is a general-purpose scalable parallel system designed to address a wide range of these applications. This paper gives an overview of the architecture and structure of SP2, discusses the rationale for the significant system design decisions that were made, indicates the extent to which key objectives were met, and identifies future system challenges and advanced technology development areas.

Performance analysis of future shared storage systems

This paper deals with the analysis and design of two important classes of computer systems: BIP (Billion Instructions Per Second) systems consisting of a few very high performance processors and KMIP (K Million Instructions Per Second) systems with hundreds of low speed processors. Each system has large, shared semiconductor memories. Simpl analytic models are developed for estimating the performance of such systems. The models are validated using simulation. They can be utilized to quickly reduce the design space and study various trade-offs. The models are applied to BIP and KMIP systems and their use is illustrated using examples.

Computer architecture: challenges and opportunities for the next decade

Computer architecture forms the bridge between application needs and the capabilities of the underlying technologies. As application demands change and technologies cross various thresholds, computer architects must continue innovating to produce systems that can deliver needed performance and cost effectiveness. Our challenge as computer architects is to deliver end-to-end performance growth at historical levels in the presence of technology discontinuities. We can address this challenge by focusing on power optimization at all levels. Key levers are the development of power-optimized building blocks, deployment of chip-level multiprocessors, increasing use of accelerators and offload engines, widespread use of scale-out systems, and system-level power optimization.

Exascale computing: the challenges and opportunities in the next decade

Supercomputing systems have made great strides in recent years as the extensive computing needs of cuttingedge engineering work and scientific discovery have driven the development of more powerful systems. In 2008, the first petaflop machine was released, and historic trends indicate that in ten years, we should be at the exascale level. Indeed, various agencies are targeting a computer system capable of 1 Exaop (10⋆⋆18 ops) of computation within the next decade. We believe that applications in many industries will be materially transformed by exascale computers.

Systems research challenges: a scale-out perspective

A scale-out system is a collection of interconnected, modular, low-cost computers that work as a single entity to cooperatively provide applications, systems resources, and data to users. The dominant programming model for such systems consists of message passing at the systems level and multithreading at the element level. Scale-out computers have traditionally been developed and deployed to provide levels of performance (throughput and parallel processing) beyond what was achievable by large shared-memory computers that utilized the fastest processors and the most expensive memory systems. Today, exploiting scale-out at all levels in systems is becoming imperative in order to overcome a fundamental discontinuity in the development of microprocessor technology caused by power dissipation. The pervasive use of greater levels of scale-out, on the other hand, creates its own challenges in architecture, programming, systems management, and reliability. This position paper identifies some of the important research problems that must be addressed in order to deal with the technology disruption and fully realize the opportunity offered by scale-out. Our examples are based on parallelism, but the challenges we identify apply to scale-out more generally.

A survey of techniques to reduce/minimize the control part/rom of a microprogrammed digital computer

In this report a survey of the research to date in microprogram minimization is presented. We discuss the works of Glushkov, Casaglia, et. al., Flynn and Rosin, Mishchenko, Schwartz, Grasselli and Montanari and Das et. al. The techniques are classified into three broad categories: the Glushkov Approach, the Ad Hoc or Engineering Approach and the Schwartz Approach. The authors views are summarized in the conclusion but the survey presents more than sufficient detail for the reader to draw his own.

Exascale computing: The challenges and opportunities in the next decade

Supercomputing systems have made great strides in recent years as the extensive computing needs of cuttingedge engineering work and scientific discovery have driven the development of more powerful systems. In 2008, the first petaflop machine was released, and historic trends indicate that in ten years, we should be at the exascale level. Indeed, various agencies are targeting a computer system capable of 1 Exaop (10⋆⋆18 ops) of computation within the next decade. We believe that applications in many industries will be materially transformed by exascale computers.

Keynote: Challenges on the Road to Exascale Computing

Supercomputing systems have made great strides in recent years as the extensive computing needs of cutting-edge engineering work and scientific discovery have driven the development of more powerful systems. In 2008, we saw the arrival of the first petaflop machine, which quickly topped the Top500 list, while also occupying the number one position on the Green500 list. Historic trends indicate that in ten years, we should be at the exascale level. We believe that applications in many industries will be materially transformed by exascale systems and will drive systems not just to 1000X in raw performance but to equally dramatic improvements in data intensive computing and real time stream processing. Meeting the exascale challenge will require significant innovation in technology, architecture and programmability. Power is a fundamental problem at all levels; traditional memory cost and performance are not keeping pace with compute potential; the storage hierarchy will have to be re-architected; networks will be a much bigger part of the system cost; reliability at exascale levels will require a holistic approach to architecture design, and programmability and ease-of-use will be an essential component to extract the promised performance at the exascale level. In this talk, I will discuss the major challenges of exascale computing, touching on the areas of technology, architecture, reliability, programmability and usability. Biography of Tilak Agerwala Tilak Agerwala is vice president, Systems at IBM Research. He is responsible for developing the next-generation technologies for IBMs systems, from microprocessors to commercial systems and supercomputers, as well as novel supercomputing algorithms and applications. Dr. Agerwala joined IBM at the T.J. Watson Research Center and has held executive positions at IBM in research, advanced development, marketing and business development. His research interests are in the area of high performance computer architectures and systems. Dr. Agerwala received the W. Wallace McDowell Award from the IEEE in 1998 for outstanding contributions to the development of high performance computers. He is a founding member of the IBM Academy of Technology. He is a Fellow of the Institute of Electrical and Electronics Engineers. He received his B.Tech. in electrical engineering from the Indian Institute of Technology, Kanpur, India and his Ph.D. in electrical engineering from the Johns Hopkins University, Baltimore, Maryland.

Designing a Scalable Parallel System: the IBM SP2*

Publisher Summary This chapter discusses that the IBM SP2 is a general purpose scalable parallel system designed to address a variety of application areas and customer environments. Generally available SP2 systems range from 2 to 128 nodes, although much larger systems, up to 512 nodes have been delivered and are successfully being used today. The nodes are the latest POWER2 technology RS/6000 processors, interconnected with a high performance multi-stage packet-switched network for inter-processor communication. Standard AIX operating system is complemented with a set of software products for system management, job management, and application development and execution in the parallel environment. The system is designed for flexibility and availability, and addresses a wide range of application areas in the high-end UNIX technical and commercial computing area. The chapter discusses the underlying philosophy that guided the design of the SP2 system and then gives an overview of the architecture and structure of the system and some of the primary system components, including wherever relevant the rationale for significant system design decisions. There is also some discussion about the system performance and future system challenges.

A Perspective on Parallel Processing

Parallel processing is one of the most important areas of computer science research. Experience with highly parallel processing is quite limited today and several architecture, systems, and software alternatives need to be investigated. In particular, much further work is required on software issues. Applications and software problems will be studied and resolved slowly as non-trivial hardware prototypes become available. Two such prototypes are currently being constructed at IBM Research. This paper has tried to place these efforts in proper perspective.