Timo Lehnigk-Emden

Low complexity LDPC code decoders for next generation standards

This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design space spanning from the decoding schedules, the node processing approximations up to the top-level decoder architecture is detailed. According to this search state-of-the-art techniques for a low complexity design have been adopted in order to meet feasible high throughput decoder implementations. An analysis of the standardized codes from the decoder-aware point of view is also given, presenting, for each one, the implementation challenges (multi rates-length codes) and bottlenecks related to the complete coverage of the standards. Synthesis results on a present 65nm CMOS technology are provided on a generic decoder architecture

A new dimension of parallelism in ultra high throughput LDPC decoding

In modern communication systems the required data rates are continuously increasing. High speed transmissions can easily generate throughputs far beyond 1 Tbit/s. To ensure error free communication, channel codes like Low-Density Parity Check (LDPC) codes are utilized. However state-of-the-art LDPC decoders can process only data rates in the range of 10 to 50 Gbit/s. This results in a gap in decoder performance which has to be closed. Therefore we propose a new ultra high speed LDPC decoder architecture. We show that our architecture significantly reduces the routing congestion which poses a big problem for fully parallel, high speed LDPC decoders. The presented 65nm ASIC implementation runs at 257 MHz and consumes an area of 12 mm2The resulting system throughput is 160 Gbit/s, it is the fastest LDPC decoder which has been published up to now. At the same time we show that extremely parallel architectures do not only increase the maximum throughput but also increase area and power efficiency in comparison to state-of-the-art decoders.

Complexity evaluation of non-binary Galois field LDPC code decoders

Forward error correction is an essential part of digital communication systems. Non-binary low-density parity-check (NB-LDPC) codes have an excellent communications performance for short block lengths. The higher the field size is, the better the communications performance is. Non-binary LDPC codes can outperform all other state-of-the-art code classes.

A Survey on LDPC Codes and Decoders for OFDM-based UWB Systems

Current UWB systems apply convolutional codes as their channel coding scheme. For next generation systems LDPC codes are in discussion due to their outstanding communications performance. LDPC codes are already utilized in the new WiMax and WiFi standards. Thus it is reasonable to investigate these codes as candidate LDPC codes for UWB. In this paper the authors present an implementation complexity and performance comparison of LDPC decoders. We will show that it is of great advantage to design new LDPC codes which are tailored to the special latency and throughput constraints of upcoming UWB systems. This new class of LDPC codes is named ultra-sparse LDPC codes. Synthesis results of WiMax, WiFi, and U-S LDPC decoders are presented based on an enhanced 65 nm CMOS process. We show that the implementation complexity of the new U-S LDPC decoders is 55% smaller, utilizing only 0.2 mm2 instead of over 0.4 mm2, while the communications performance of all observed LDPC codes are almost identical under all the considered UWB simulation conditions.

Fast convergence algorithm for LDPC Codes

Low-density parity-check (LDPC) codes are one of the most powerful codes known today. They are decoded iteratively by a message passing algorithm. There exist many different update schemes of the exchanged messages. The major difference of all update schemes is the convergence speed, i.e. the achieved communications performance for a limited number of iterations. This paper presents a new decoding algorithm which efficiently utilizes the encoder property of linear encodable LDPC codes. The basic idea is to interpret the LDPC encoder as an encoder with puncturing unit which opens as well the door for hybrid ARQ schemes. The presented new decoding algorithm shows a faster convergence behavior than state of art decoding schemes and it results in a lower error floor

Enhanced Channel Coding for OFDM-based UWB Systems

In this paper the authors present an enhanced channel coding scheme and architecture providing LDPC codes for the use in future generations of the WIMEDIA UWB industry standard. Main emphasis is put on the development of a low complex LDPC code which provides a throughput of at least 1.1 Gbit/s, with a reduced number of iterations even up to 1.6 Gbit/s. By using such an enhanced channel coding scheme the range or the data rate of the WIMEDIA UWB system could be remarkably increased with a limited increase in implementation complexity with respect to silicon area

Syndrome based check node processing of high order NB-LDPC decoders

Non-binary low-density parity-check codes have superior communications performance compared to their binary counterparts. However, to be an option for future standards, efficient hardware architectures must be developed. State-of-the-art decoding algorithms lead to architectures suffering from low throughput and high latency. The check node function accounts for the largest part of the decoders overall complexity. In this paper a new, hardware aware check node algorithm is proposed. It has state-of-the-art communications performance while reducing the decoding complexity. Moreover the presented algorithm allows for partially or even fully parallel processing of the check node operations which is not applicable with currently used algorithms. It is therefore an excellent candidate for future high throughput hardware implementations.

Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding

In modern communications systems the required data rates are continuously increasing. Especially consumer electronic applications like video on demand, IP-TV, or video chat require large amounts of bandwidth. Already today’s applications require throughputs in the order of Gigabits per second and very short latency. Current mobile communications systems achieve 1 Gbit/s (LTE [1]) and wired transmission enables even higher data rates of 10 Gbit/s (e.g., Thunderbolt [2], Infiniband [3]) up to 100 Gbit/s. For the future it is clearly expected that even higher data rates become necessary. Early results show throughputs in the order of 100 Tbit/s [4] for optical fiber transmissions.

Low-complexity iteration control for MIMO-BICM systems

Air bandwidth is a precious resource for wireless communication. Multiple-antenna (MIMO) systems enable an increase in channel capacity without increasing the air bandwidth. An iterative demapping and decoding at the receiver improves the communications performance remarkably. However, MIMO demapping and channel decoding have a high computational complexity. Energy consumption, latency and throughput of a hardware implementation strongly depend on the number of iterations. Iteration control techniques are very efficient to reduce the average number of iterations thus increasing decoder throughput and reducing energy consumption and average decoding latency. To the best of our knowledge, we present the first analysis of iteration control in MIMO bit interleaved coded modulation systems. We introduce a novel stopping metric for iteration control, which outperforms existing stopping metrics for middle and high signal-to-noise ratios. Additionally, we analyze state-of-the-art stopping metrics with respect to their algorithmic complexity in due consideration of a later hardware implementation.

Implementation Issues of Turbo Synchronization with Duo-Binary Turbo Decoding

The transmission over a wireless channel results in timing, frequency and phase offsets. To circumvent the severe losses of communications performance caused by these offsets a sophisticated synchronization is mandatory. Synchronization is typically performed only once prior to the channel decoding. In this paper the authors present an FPGA implementation of a joint iterative decoder and synchronizer, which is also referred to as turbo synchronizer. We investigate the additional costs of turbo synchronization in terms of implementation complexity with a 16-state duo-binary turbo decoder. Furthermore we present the communications performance of the turbo synchronizer taking the implementation losses into account.