Fadi Y. Busaba

Self-checking combinational circuit design for single and unidirectional multibit error

This article presents novel input and output encoding techniques such that the resulting circuit is bidirectional error-free. The circuit can be fully optimized and any types of gates can be used. These schemes are used to design the functional part of a self-checking circuit. The input encoding algorithm can be applied to any circuit without significantly increasing the input lines. The output encoding technique involves graph-embedding which is done with heuristic method of polynomial complexity. The heuristic technique produces nearly optimal output encoding. Previously published work restrict the types of gates used in the circuit to non-inversion gates (AND/OR), and use inverters only at the inputs. The proposed techniques have a clear advantage over the currently available techniques because they allow the use of any types of gates. These techniques do not necessarily increase the overhead when applied to different MCNC benchmark circuits as the experimental results indicate. The only restriction is that either the inputs or the outputs have to be symbolic, and the two-level description of a circuit has to be given.

Input and output encoding techniques for on-line error detection in combinational logic circuits

Presents techniques for designing arbitrary combinational circuits so that any single stuck-at fault will result in either single bit error or unidirectional multibit errors at the output. An input encoding algorithm and an output encoding algorithm that ensure that every fault at the input will either produce single bit error or unidirectional multibit errors at the output are proposed. If there are no input faults which produce bidirectional error, no internal stuck-at fault will result in such an error irrespective of the way the circuit is implemented. The proposed techniques have been applied to MCNC benchmark circuits and the overhead is estimated.<<ETX>>

An approach for designing self-checking logic using residue codes

It is generally agreed now that the major portion of faults in logic system are not of permanent nature. Current testing strategies are incapable of detecting nonpermanent faults. The characteristics of such faults requires that logic circuits be designed in a way so that if there is a fault in the circuit, its effect will be detected during the normal operation of the circuit, i.e. the circuits be self-checking. In this paper the authors propose two rules based on the mode 3 residue coding scheme for designing circuits for online error detection.<<ETX>>

VHDL description of self-checking logic circuits

The mainstream of current digital circuit design strategy is top-down, where the design process is divided into many phases. A designer starts with a high level description of a circuit, e.g. VHDL, and goes through the design phases to reach mask layout level. This paper develops a set of rules that can be applied to any VHDL description of a logic circuit such that the synthesized gate level circuit is self-checking. Therefore, for a given VHDL description of a logic circuit these rules will transform/modify the existing VHDL code into another equivalent code such that the resulting synthesized circuit will be self-checking. Such a VHDL code is called self-checking VHDL.

A unified approach for off-line and on-line testing of VLSI systems

BIST (Built-in self-test) techniques are often used to improve the testability of VLSI systems. Self-checking techniques are used to detect the presence of a fault in a system during normal operation. BIST techniques can be used only in on-line mode, whereas self-checking enables on-line resting. This paper presents a new approach for combining BIST and self-checking, which utilizes the resources of both to enhance the testability of VLSI systems.

A graph coloring based approach for self-checking logic circuit design

This paper presents a technique for designing self-checking logic circuits by using residue codes. There are no restrictions or assumptions made about the implementation of the circuit. For any single stuck-at fault that causes bi-directional error at the output, all pairs of faulty output lines that show bi-directional errors are identified. Based on the bi-directional dependency between the outputs, a minimum set of residue weights are assigned to the output lines so that any error at the outputs can be detected.

An Approach for Self-Checking Realization of Interacting Finite State Machines

This paper presents a technique for designing interacting finite state machines which will be totally self-checking for any single stuck-at fault. In the proposed technique m-out-of-n codes are used for both primary output and state assignments. In addition, the next state logic (NSL) for each submachine and the output logic (OL) are realized such that any single stuck-at fault results in either single bit error or unidirectional multibit error at the output. The proposed technique does not have any restriction on the way the NSL and the OL are implemented.

On interacting finite state machine design with self-checking capability

A technique for designing interacting finite-state machines that will be totally self-checking for any single stuck-at fault is presented. M-out-of-n codes are used for both primary output and state assignments. The next state logic (NSL) for each submachine and the output logic (OL) realized are such that any single stuck-at fault results in either single bit error or unidirectional multibit error at the output. An m-out-of-n checker is added to check the validity of the output lines so that any fault can be detected online by the checker.

Design of self-checking interacting FSMs for multiple faults

This paper introduces new technique for designing self-checking interacting machines for on-line detection of multiple stuck-at faults. The only assumption is that each constituent submachine of a composite submachine can have only one single stuck-at fault. The proposed technique adds checkers at the embedded interfaces between the submachines.<<ETX>>

On Self-Checking Design of CMOS Circuits for Multiple Faults

A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary MOS) designs for multiple faults is presented in this paper. The existing techniques for self checking design consider only single faults, and suffer from high silicon area overhead. The multiple faults considered in this paper are multiple breaks, multiple transistors stuck-offs and multiple transistors stuck-ons. Starting from FCMOS design, small modifications (addition of two-weak transistors) make the original circuit totally self-checking. Experiemntal results show the overhead, delay and power consumption for the proposed technique. This paper also presents a technique for designing multistage TSC FCMOS circuits.