Timwah Luk

3D Modeling of electromigration combined with thermal–mechanical effect for IC device and package

This paper studies the numerical simulation method for electromigration in IC device and solder joint in a package under the combination of high current density, thermal load and mechanical load. The three dimensional electromigration finite element model for IC device/interconnects and solder joint reliability are developed and tested. Numerical experiment is carried out to obtain the electrical, thermal and stress fields with the migration failure under high current density loads. The direct coupled analysis and in-direct coupled analysis that include electrical, thermal and stress fields are investigated and discussed. The viscoplastic Anand constitutive material model with both SnPb and SnAgCu lead- free solder materials is considered in the paper. An IC device is studied to show the modeling methodology and the comparison with previous test data. A global CSP package with PCB is modeled using relative coarse elements. In order to reduce the computational costs and to improve the calculation accuracy, a refined mesh sub-model is constructed. The sub-model technique is studied in a direct and indirect coupled multiple fields. The comparison of voids generation through numerical example in this paper and previous experimental result is given.

Thermosonic Wire Bonding Process Simulation and Bond Pad Over Active Stress Analysis

In this paper, a transient non-linear dynamic finite element framework is developed, which integrates the wire bonding process and the silicon devices under the bond pad. Two major areas are addressed: one is the impact of the assembly 1/sup st/ wire bonding process and another one is the impact of device layout below the bond pad. Simulation includes the ultrasonic transient dynamic bonding process and the stress wave transferred to the bond pad device and silicon in the 1/sup st/ bond. The Pierce strain rate dependent model is introduced to model the impact strain hardening effect. Ultrasonic amplitude and frequency are studied and discussed for the bonding process. In addition, different layouts of device metallization under the bond pad are analyzed and discussed for the efforts to reduce the dynamic impact response of the bond pad over active (BPOA) design. Modeling discloses the stress and deformation impacts to both wire bonding and pad below the device with strain rate, different ultrasonic amplitudes and frequencies, different friction coefficients, as well as different bond pad thickness and device layout under the pad. The residual stress, after cooling down to a lower temperature, is discussed for the impact of substrate temperature.

Thermosonic wire bonding process simulation and bond pad over active stress analysis

In this paper, a transient nonlinear dynamic finite element framework is developed, which integrates the wire bonding process and the silicon devices under bond pad. Two major areas are addressed: one is the impact of assembly 1st wire bonding process and another one is the impact of device layout below the bond pad. Simulation includes the ultrasonic transient dynamic bonding process and the stress wave transferred to bond pad device and silicon in the 1st bond. The Pierce strain rate dependent model is introduced to model the impact stain hardening effect. Ultrasonic amplitude and frequency are studied and discussed for the bonding process. In addition, different layouts of device metallization under bond pad are analyzed and discussed for the efforts to reduce the dynamic impact response of the bond pad over active design. Modeling discloses the stress and deformation impacts to both wire bonding and pad below device with strain rate, different ultrasonic amplitudes and frequencies, different friction coefficients, as well as different bond pad thickness and device layout under pad. The residual stress, after cooling down to a lower temperature, is discussed for the impact of substrate temperature.

Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models

A novel macro model approach for modeling ESD MOS snapback is introduced. The macro model consists of standard components only. It includes a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a resistor for substrate resistance. No external current source, which is essential in most publicly reported macro models, is included since both BSIM3vs and VBIC have formulations built in to model the relevant effects. The simplicity of the presented macro model makes behavior languages, such as Verilog-A, and special ESD equations not necessary in model implementation. This offers advantages of high simulation speed, wider availability, and less convergence issues. Measurement and simulation of the new approach indicates that good silicon correlation can be achieved.

A Data Mining Algorithm for Monitoring PCB Assembly Quality

A pattern clustering algorithm is proposed in this paper as a statistical quality control technique for diagnosing the solder paste variability when a huge number of binary inspection outputs are involved. To accommodate this goal, a latent variable model is first introduced and incorporated into classical logistic regression model so that the interdependencies between measured physical characteristics and their relationship to the final solder defects can be explained. This probabilistic model also allows a maximum-likelihood principal component analysis (MLPCA) method to recognize the dimension of systematic causes contributing to solder paste variability. The correlated measurement variables are then projected onto the reduced latent space, followed by an appropriate clustering approach over the inspected solder pastes for variation interpretation and quality diagnosing. An application to a real stencil printing process demonstrates that this method facilitates in identifying the root causes of solder paste defects and thereby improving PCB assembly yield.

Wire bonding capillary profile and bonding process parameter optimization simulation

In this paper, a methodology for wire bonding parameter modeling is developed, which considers the capillary, FAB and device on silicon. The impact of capillary profile and bonding process parameters which include ball diameter, bonding temperature and bond wire material properties are studied to optimize the wire bonding assembly process. Finally, the comparison of the results with and without the modeling optimization shows that the probability of bonding failure is reduced after the wire bonding process is optimized.

Trends of Power Electronic Packaging and Modeling

A review of recent advances in power electronic packaging is presented based on the development of power device integration. The presentation will cover in more detail how advances in both semiconductor content and power advanced package design and materials have co-enabled significant advances in power device capability during recent years. Extrapolating the same trends in representative areas for the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with new power packaging development, the role of modeling is key to assure successful package design. An overview of the power package modeling is presented. Challenges of power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed.

Simulation and Analysis for Typical Package Assembly Manufacture

The manufacturing process for package assembly is a key to assuring the reliability and quality of the semiconductor products. There are a significant number of challenging mechanics problems in assembly manufacturing process that may lead to the failure of die, delamination and package cracking. Identifying potential root causes of quality and reliability problems during the development of an assembly process and during package design is very important; it can reduce scrap during manufacturing, save development time, as well as help insure the product meets the requirements of customers. Simulation can find the root cause quickly and accurately, leading to reduced time and cost. It enables experiments that are too costly to be done by empirical methods. Using simulation we can find the conditions that optimize cost, performance and reliability under different sets of conditions. This paper focuses on modeling and simulation for typical package assembly manufacture processes which have large impact to the product quality and reliability. A finite element framework is developed to simulate the assembly package manufacturing process utilizing the ANSYS software platform. The framework tools are utilized to maximize the robustness of the assembly process in order to eliminate reliability issues, fast run time and minimize costs in development and from manufacturing scrap.

Simulation and experimental analysis for a ball stitch on bump wire bonding process above a laminate substrate

This study focuses on a ball stitch on bump (BSOB) wire bonding process above a laminate substrate by modeling and experiment. The goals of our study are: (1) to determine the stress and deformation mechanism of BSOB wire bonding process on laminate substrate; (2) to understand the impact of wire bonding parameters. The simulation includes the ultrasonic transient dynamic bonding process, and the stress wave transferred to the interface between bond structure and laminate substrate. Different laminate material parameters are studied for the optimized solution. Different ultrasonic parameters of bonding force and frequency are studied and discussed for the effects of bonding process on laminate substrate structures with partial supports. Experimental test work includes a DOE study with different parameters of ultrasonic power and bonding force. Finally, the comparison of modeling and experimental results is provided

Systematic evaluation of die thinning application in a power SIPs by simulation

In this paper, a lead frame based system in package (SIP) for power management is examined. This package is built using multiple die types including power IGBTs, diodes, and IC controllers. To maximize product performance the power components use an ultra thin back grind. Thin dies minimize RDS(on), maximize thermal performance, and minimize the board standoff height by allowing the package to be thinner. However, the ultra thin die could be a potential risk for die cracking if it is done without careful evaluation, especially for die thickness as thin as 90 mum and 50 mum. So it is critical to understand the impact of thinning dies on the reliability of the product in assembly manufacture and vary reliability tests. Modeling and simulation with a smaller amount of empirical testing is a good way to evaluate this thin die application quickly and at a lower cost. Therefore, the objective of this paper is to fully investigate the thin die application in a power SIP with systematic simulation and analysis before real application. A large complicated and advanced 3D FEA model framework is developed for the SIP. The major modeling and evaluation work is categorized into two areas: One is to check the impact of the thin die on different assembly processes. The other is to simulate the major reliability tests such as temperature cycle (TMCL) and component-level reflow process. Comprehensive evaluation and analysis of the modeling and simulation results for the thin die application to a Fairchild power SIP are presented