Ting-Chen Wei

All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad

In this paper, a detection and estimation scheme and its architecture design for synchronization in 60 GHz indoor wireless transmission are presented. With the complementary Golay sequence based preamble structure, the proposed synchronization scheme is designed to detect the preamble and symbol boundary, estimate the frequency offset within a unified architecture. For the very high sampling speed at 60 GHz transmission, the architecture is designed as 8 ×-parallelism with feed-forward data path. This architecture supports the single carrier (SC) and orthogonal frequency-division multiplexing (OFDM) transmissions of both IEEE 802.15.3c and IEEE 802.11ad standards. The synchronization module is implemented as a part of a digital baseband receiver for IEEE 802.15.3c. The tolerance of maximum frequency offset is about 114.58 ppm and 171.87 ppm for SC and OFDM mode, respectively. The implementation result shows that it takes about 0.84 mm2 of area (equivalent to 307 k gate counts). The power consumption is about 59 mW in SC mode and 96 mW in OFDM (HSI) mode when operating at 1.76 GHz and 2.64 GHz chip rate, respectively.

A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band

In this paper, a digital time domain equalizer (TDE) for 60 GHz radio frequency transmission systems is presented. Significantly, the TDE supports both single carrier (SC) and orthogonal frequency-division multiplexing (OFDM) operation modes for digital baseband receiver. In order to improve the performance, the proposed TDE adopts Golay sequence aided one-shot channel estimation and modified multi-path interference cancellation (MPIC) equalization. Targeting on the line-of-sight (LOS) channel characteristic, MPIC is simplified with single-tap for complexity reduction. From the area efficiency point of view, both SC and OFDM modes are designed within a single hardware to yield 99% of area sharing. The Golay-MPIC TDE structure is realized as feed-forward data path with 8X-parallelism to achieve 2.64 GS/s at 330 MHz clock rate. The Golay-MPIC TDE is fabricated as a part of a digital baseband with 65 nm 1P9M general purpose process. The area of Golay-MPIC TDE occupies 1.05 mm2 with 405 K gate counts. Besides, the power dissipations for SC and ODFM modes are 56.71 mW@220 MHz (1 V) and 91.29 mW@330 MHz (1.1 V), respectively. Finally, the chip can provide the maximum throughput 15.84 Gb/s (2.64 GS/s with 64-QAM modulation).

Blind Mode/GI Detection and Coarse Symbol Synchronization for DVB-T/H

In a non-data-aided (NDA) broadcasting system such as DVB-T/H, blind transmission mode, guard interval (GI) length detection and coarse symbol synchronization (CSS) play important roles to estimate the transmitted OFDM symbol parameters and start the synchronization processes. In this paper, a single hardware and division-free architecture, modified from normalized-maximum-correlation (NMC) architecture, for DVB-T/H blind mode/GI detection and coarse symbol synchronization (CSS) is proposed. By adopting the proposed twister memory access scheme and sequential blind mode detection scheme, the architecture reduces 33% of memory costs and at most 58.18% mode detection latencies.

Low complexity synchronization design of an OFDM receiver for DVB-T/H

In this paper, an OFDM baseband receiver for DVB-T/H is presented. The receiver contains four synchronizations, an OFDM symbol synchronization, a carrier synchronization, a sampling clock synchronization and a scattered pilots synchronization. This paper proposes several novel designs to reduce the synchronization latency and hardware complexity. The carrier and clock synchronization loops are fully digitalized schemes. The scattered pilots synchronization adopts a two stages scheme to reduce the detection latency. In addition, the pre-filling scheme reduces the latency of channel estimation. The design result shows that the equivalent gate count is about 810 K gates including 102.8 KB memory.

A SC/HSI dual-mode baseband receiver with frequency-domain equalizer for IEEE 802.15.3c

In this paper, an 8X-parallelism digital baseband receiver is proposed for IEEE 802.15.3c application. The baseband receiver consists of all-digital synchronization, radix-16 FFT and LS-LMS equalizer modules. It supports SC and HSI dual-mode in IEEE 802.15.3c with single hardware for area efficiency. The chip is implemented with 65 nm 1P9M process. The fabricated area is 12.96 mm2 with 3463 K gate counts. The post-layout verification shows the throughput rate under QPSK modulation achieves 3.52 Gb/s and 5.28 Gb/s for SC mode (220 MHz) and HSI mode (330 MHz), respectively.

A SC/OFDM dual mode frequency-domain equalizer for 60GHz multi-gbps wireless transmission

This work proposes an adaptive frequency-domain equalizer (FDE) for single carrier and OFDM indoor over Gbps data rate wireless receiver. System simulation and specifications are based on the IEEE 802.15.3c standard. The proposed LS-LMS FDE uses low computational complexity Least-Mean-Square (LMS) algorithm with Least-Square (LS) channel estimation to accelerate the convergence speed. The FDE can be used for dual mode (SC and HSI) Wireless Personal Area Networks (WPAN) system. The simulation results show that the LS-LMS FDE can achieve 1.32∗10−4 BER in SC mode and 6.55∗10−3 in HSI mode (both uncoded) at SNR 14 dB. The total area is about 415K gate-count with 69% shared among single carrier and OFDM mode except 2 FFT. The power consumption is only 81.27 mW when working at 400MHz.

An IEEE 802.15.3c/802.11ad compliant SC/OFDM dual-mode baseband receiver for 60 GHz Band

In this paper, a dual-standard, dual-mode baseband receiver for 60 GHz wireless communication is presented. The receiver is designed to support SC and OFDM modes for both IEEE 802.15.3c and IEEE 802.11ad standards. The receiver is integrated with all-digital synchronization, radix-16 FFT, phase noise cancellation and low-complexity time-domain equalizer for line-of-sight channel application. The hardware utilization achieves 70% by leveraging hardware sharing between two modes and two standards for area efficiency. The receiver is implemented with 65 nm 1P9M process in 7.95 mm2 core area. With feed-through architecture, the throughput rate supports up to 7.04 Gb/s and 15.84 Gb/s for SC mode (220 MHz) and OFDM mode (330 MHz), respectively.

Symbol and carrier frequency offset synchronization for IEEE802.16e

IEEE 802.16e standard has been proposed as a specification for the next generation wireless communication system. Synchronization plays an important role for a wireless receiver. Because the repetition of preamble is unapparent in orthogonal frequency division multiple access (OFDMA) modulation mode, a correlation based scheme like match filter is used to estimate the symbol boundary and integer carrier frequency offset (ICFO). In this paper, an effective hardware architecture of correlation is proposed. By adopting the modified algorithm, mass of multipliers are removed from hardware implementation. Design results show that 56 % area reduction and 64% power saving are achieved. Moreover, a ping-pong algorithm is proposed to increase the accuracy of ICFO synchronization about two orders at most.

Two-Stage Scattered Pilot Synchronization with Channel Estimation Scattered Pilots Pre-Filling for DVB-T/H

In this paper a two-stage fast scattered pilot synchronization (SPS) scheme is proposed to increase the reliability of scattered pilot synchronization in DVB-T/H. A channel estimation scattered pilots pre-fllling scheme is added to the two-stage fast scattered pilot synchronization scheme and reduces at least one symbol time to the demapping process. By using multi-stage PB-PB (Power-Based) fast scattered pilot synchronization scheme, the performance and reliability is improved with less hardware cost than single stage CB (correlation-based) fast scattered pilot synchronization scheme.

Low Power and Power Aware Design for DVB-T/H Baseband Inner Receiver

From hardware point of view, system and RTL low power and power aware design techniques are applied to the DVB-T/H baseband inner receiver. In RTL design, we use pre-computation, differential encoding, hardware sharing, time-multiplexing R/W of memory, low power arithmetic architecture so that each block can reduce power from 3% to 26%. In system level, the proposed DPM (dynamic power manager) is a power control unit for our system. When the system enters the offset tracking mode, the DPM controls the power states of system blocks between the GI (guard interval) period and symbol period. The power reduction ratio ranges from 3%~20% (it depends on the Gl mode). Moreover, a predicted phase scheme is proposed to provide the initial phase offset for the start of symbol period during offset tracking mode. The overall reduction for synchronization loop is about 50% in both hardware area and power.